Changeset 113 for anr/task-5.tex

Timestamp:

Feb 8, 2010, 11:40:38 PM (15 years ago)

Author:

coach

Message:

IA: updated pour XILINX

File:

• anr/task-5.tex (modified) (4 diffs)

anr/task-5.tex

@@ -5 +5 @@
 \let\UPMC\leader
 \let\TIMA\enable
-\let\ALTERA\enable
+\let\XILINX\enable
 \end{taskinfo}
 %
@@ -71 +71 @@
         \setMacroInAuxFile{hpcPlbBridge}
         The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model.
-    \itemL{9}{18}{h}{\Saltera}{HPC hardware \altera}{0:0:0}
+    \itemL{9}{18}{h}{\Supmc}{HPC hardware \altera}{1:2:0}
         \setMacroInAuxFile{hpcAvalonBridge}
         The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model.
@@ -82 +82 @@
 It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library.
     \begin{livrable}
-    \itemL{18}{36}{x}{\Supmc}{CSG support for \ganttlf reconfiguration}{0:0:2}
+    \itemL{24}{36}{x}{\Supmc}{CSG support for \ganttlf reconfiguration}{0:0:2}
         Modification of CSG software to support statically reconfigurable task.
     \itemL{18}{36}{x}{\Stima}{CSG module for \ganttlf dynamic reconfiguration}{0:6:12}
@@ -99 +99 @@
         reconfiguration dedicated features (reconfiguration time of regions, variable
         number of coprocessors).
+    \itemL{24}{36}{d}{\Sxilinx}{optimisation for \ganttlf \xilinx dynamic reconfiguration}{0:0:1}
+        \xilinx will work with \tima in order to better take into account during
+        partitioning decisions specific constraints due to partial reconfiguration process.
+        The delivrable is a document describing the \xilinx specific constraints.
     \end{livrable}
-\item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board
-    with its PCI/X IP. These boards are dedicated to the COACH HPC development.
-    They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT.
-    \begin{livrable}
-    \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards.
-    \end{livrable}
+%\item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board
+%   with its PCI/X IP. These boards are dedicated to the COACH HPC development.
+%   They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT.
+%   \begin{livrable}
+%   \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards.
+%   \end{livrable}
 \end{workpackage}