source: anr/task-5.tex @ 40

\begin{taskinfo}
\let\UPMC\leader
\let\TIMA\enable
\let\ALTERA\enable
\end{taskinfo}
%
\begin{objectif}
This task pools the features dedicated to HPC system design. It is described on
figures~\ref{coach-flow} and \ref{archi-hpc}. It consists in
\begin{itemize}
\item Helping the HPC designer to find a good partition of the initial application
    (figure~\ref{archi-hpc}.
\item Providing communication schemes between the software part runing on the PC and the
FPGA-SoC.
\item Implementing the communication scheme at all levels: partition help, software
implementation both on the PC and in the operating system of the FPGA-SoC, hardware.
\item FPGA reconfiguration. \mustbecompleted{FIXME:TIMA}
\end{itemize}
The low level hardware transmission support will be the PCI/X bus which allows high bit-rate
transfers. The reasons of this choices are that both ALTERA and Xilinx provide PCI/X IP for
their FPGA and that GPU HPC softwares use also it.
This will allow us at least to be inspired by GPU communication schemes and may be to reuse
parts of the GPU softwares.
\end{objectif}
%
\begin{workpackage}{D5}
\item This \ST is the definition of the communication schemes as a software API
    (Application Programing Interface) between the application part running on the PC and
    the application part running on the FPGA-SoC.
    \begin{livrable}
    \item{}{0}{6}{d}{\Supmc}{HPC communication API} User refernce manual describing the API.
        \global\edef\hpcCommApi{\name}
    \end{livrable}
\item This \ST consists in helping to partition the application.
    It is a library implementing the communication API with features to profile
    the partitioned application.
    \begin{livrable}
    \item{}{6}{12}{x}{\Supmc}{HPC partionning helper} A library implementing the communication
        API defined in the {\hpcCommApi} delivrable.
    \end{livrable}
\item This \ST deals with the implementation of the communication API on the both sides (PC
    part and FPGA-SoC).
    \begin{livrable}
    \item{}{12}{21}{x}{\Supmc}{HPC API for Linux PC} The PC part of the HPC communication API
        that comminicates with the FPGA-SOC, a library and probably a LINUX module.
    \item{}{12}{21}{x}{\Supmc}{HPC API for MUTEK OS} The FPGA-SoC part of the communication API, a
        driver.\global\edef\hpcMutekDriver{\name}
    \item{}{21}{24}{x}{\Stima}{HPC API for DNA OS} Port of the {\hpcMutekDriver} driver on the DNA OS.
    \end{livrable}
\item This \ST deals with the implementation of hardware required by the COACH
    architectural template for using the PCI/X IP of \altera and \xilinx.
    \begin{livrable}
    \item{}{9}{18}{h}{\Stima}{HPC hardware \xilinx}
        \setMacroInAuxFile{hpcPlbBridge}
        The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model.
    \item{}{9}{18}{h}{\Saltera}{HPC hardware \altera}
        \setMacroInAuxFile{hpcAvalonBridge}
        The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model.
    \end{livrable}
\item This \ST deals with the dynamic reconfiguration of an FPGA.
    \begin{livrable}
    \item{}{18}{30}{x}{\Stima}{dynamic reconfiguration \ganttlf DNA drivers}
        \global\edef\hpcDynconfDriver{\name}
        \mustbecompleted{FIXME:TIMA ....}
    \item{}{30}{36}{x}{\Supmc}{dynamic reconfiguration \ganttlf MUTEK drivers}
        Port of the {\hpcDynconfDriver} \mustbecompleted{FIXME:TIMA driver} on the MUTEK OS.
    \item{}{24}{36}{x}{\Supmc}{CSG support for \ganttlf dynamic reconfiguration}
        \mustbecompleted{FIXME:TIMA ....}
    \item{}{18}{36}{x}{\Stima}{PC support for \ganttlf dynamic reconfiguration}
        \mustbecompleted{FIXME:TIMA ....}
    \end{livrable}
\item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board
    with its PCI/X IP. These boards are dedicated to the COACH HPC development.
    They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT.
    \begin{livrable}
    \item{}{0}{6}{m}{\Saltera}{HPC development boards} Two PCI/X FPGA boards.
    \end{livrable}
\end{workpackage}