source: anr/task-5.tex @ 60

Last change on this file since 60 was 59, checked in by coach, 15 years ago

IA: renumerotation des taches

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1% vim:set spell:
2% vim:spell spelllang=en:
3
4\begin{taskinfo}
5\let\UPMC\leader
6\let\TIMA\enable
7\let\ALTERA\enable
8\end{taskinfo}
9%
10\begin{objectif}
11This task pools the features dedicated to HPC system design. It is described on
12figures~\ref{coach-flow} and \ref{archi-hpc}. It consists in
13\begin{itemize}
14\item Helping the HPC designer to find a good partition of the initial application
15    (figure~\ref{archi-hpc}).
16\item Providing communication schemes between the software part running on the PC and the
17FPGA-SoC.
18\item Implementing the communication scheme at all levels: partition help, software
19implementation both on the PC and in the operating system of the FPGA-SoC, hardware.
20\item Providing support for dynamic partial reconfiguration of \xilinx FPGA in order to optimize FPGA ressource usage.
21\end{itemize}
22
23The low level hardware transmission support will be the PCI/X bus which allows high bit-rate
24transfers. The reasons of this choices are that both ALTERA and Xilinx provide PCI/X IP for
25their FPGA and that GPU HPC softwares use also it.
26This will allow us at least to be inspired by GPU communication schemes and may be to reuse
27parts of the GPU softwares.
28
29\end{objectif}
30%
31\begin{workpackage}
32\item This \ST is the definition of the communication schemes as a software API
33    (Application Programing Interface) between the application part running on the PC and
34    the application part running on the FPGA-SoC.
35    \begin{livrable}
36    \itemL{0}{6}{d}{\Supmc}{HPC communication API}{1.0:0:0}
37        \setMacroInAuxFile{hpcCommApi}
38        User reference manual describing the API.
39    \end{livrable}
40\item This \ST consists in helping to partition applications.
41    It is a library implementing the communication API with features to profile
42    the partitioned application.
43%FIXME (Olivier) pour moi, on veut un outil de profiling pour partitionner l'application.
44% It is a profiling (or simulation) library implementing the communication API
45
46    \begin{livrable}
47    \itemL{6}{12}{x}{\Supmc}{HPC partionning helper}{1:0:0}
48        A library implementing the communication API defined in the {\hpcCommApi} delivrable.
49    \end{livrable}
50\item This \ST deals with the implementation of the communication API on the both sides (PC
51    part and FPGA-SoC).
52    \begin{livrable}
53    \itemL{12}{21}{x}{\Supmc}{HPC API for Linux PC}{0:3:0}
54        The PC part of the HPC communication API that comminicates with the FPGA-SOC, a
55        library and probably a LINUX module.
56    \itemL{12}{21}{x}{\Supmc}{HPC API for MUTEK OS}{0:3:0}
57        \setMacroInAuxFile{hpcMutekDriver}
58        The FPGA-SoC part of the communication API, a driver.
59    \itemL{21}{24}{x}{\Stima}{HPC API for DNA OS}{0:3:0}
60        Port of the {\hpcMutekDriver} driver on the DNA OS.
61    \itemL{24}{33}{x}{\Supmc}{HPC API}{0:0:1}
62        Maintenance work of HPC API for both Linux PC and MUTEK OS.
63    \end{livrable}
64\item This \ST deals with the implementation of hardware and SystemC modules
65    required by the COACH architectural template for using the PCI/X IP of \altera and \xilinx.
66    \begin{livrable}
67    \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0}
68        \setMacroInAuxFile{hpcPlbBridge}
69        The synthesizable VHDL description of a PLB/VCI bridge and its corresponding SystemC model.
70    \itemL{9}{18}{h}{\Saltera}{HPC hardware \altera}{0:0:0}
71        \setMacroInAuxFile{hpcAvalonBridge}
72        The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model.
73    \itemL{9}{24}{h}{\Supmc}{PCI/X traffic generator}{1:1:0}
74        The SystemC description of a component that generates PCI/X traffic. It is
75        required to prototype FPGA-SoC dedicated to HPC.
76    \end{livrable}
77
78\item This \ST consists in integrating dynamic partial reconfiguration of \xilinx FPGA in the CSG design flow.
79It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library.
80    \begin{livrable}
81    \itemL{18}{36}{x}{\Supmc}{CSG support for \ganttlf dynamic reconfiguration}{0:0:2}
82        Extension of the \xilinx architectural template ({\csgAllArch}) in order to
83        integrate dynamic partial reconfiguration regions.
84        Modification of CSG software to support the extended \xilinx template.
85    \itemL{18}{30}{x}{\Stima}{dynamic reconfiguration \ganttlf DNA drivers}{0:2:3}
86        \setMacroInAuxFile{hpcDynconfDriver}
87            The drivers required by the DNA OS in order to manage dynamic partial
88        reconfiguration inside the SoC-FPGA.
89    \itemL{30}{36}{x}{\Supmc}{dynamic reconfiguration \ganttlf MUTEK drivers}{0:0:1}
90        Port of the {\hpcDynconfDriver} drivers on the MUTEK OS.
91    \itemL{24}{36}{x}{\Stima}{HPC profiler for \ganttlf dynamic reconfiguration}{0:0:6}
92        Extension of the HPC partionning helper in order to integrate dynamic partial
93        reconfiguration dedicated features (reconfiguration time of regions, variable
94        number of coprocessors).
95    \end{livrable}
96\item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board
97    with its PCI/X IP. These boards are dedicated to the COACH HPC development.
98    They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT.
99    \begin{livrable}
100    \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards.
101    \end{livrable}
102\end{workpackage}
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