Changeset 59 for anr/task-5.tex

Timestamp:

Feb 2, 2010, 3:06:02 AM (14 years ago)

Author:

coach

Message:

IA: renumerotation des taches

File:

• anr/task-5.tex (modified) (3 diffs)

anr/task-5.tex

@@ -26 +26 @@
 This will allow us at least to be inspired by GPU communication schemes and may be to reuse
 parts of the GPU softwares.
-
 
 \end{objectif}
@@ -63 +62 @@
         Maintenance work of HPC API for both Linux PC and MUTEK OS.
     \end{livrable}
-\item This \ST deals with the implementation of hardware required by the COACH
-    architectural template for using the PCI/X IP of \altera and \xilinx.
+\item This \ST deals with the implementation of hardware and SystemC modules
+    required by the COACH architectural template for using the PCI/X IP of \altera and \xilinx.
     \begin{livrable}
     \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0}
@@ -72 +71 @@
         \setMacroInAuxFile{hpcAvalonBridge}
         The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model.
+    \itemL{9}{24}{h}{\Supmc}{PCI/X traffic generator}{1:1:0}
+        The SystemC description of a component that generates PCI/X traffic. It is
+        required to prototype FPGA-SoC dedicated to HPC.
     \end{livrable}
+
 \item This \ST consists in integrating dynamic partial reconfiguration of \xilinx FPGA in the CSG design flow.
 It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library.
-
     \begin{livrable}
-    \itemL{18}{36}{x}{\Stima}{CSG support for \ganttlf dynamic reconfiguration}{0:8:12}
-        Extension of the \xilinx architectural template ({\csgAllArch})
-in order to integrate dynamic partial reconfiguration regions.
-Modification of CSG software to support the extended \xilinx template.
+    \itemL{18}{36}{x}{\Supmc}{CSG support for \ganttlf dynamic reconfiguration}{0:0:2}
+        Extension of the \xilinx architectural template ({\csgAllArch}) in order to
+        integrate dynamic partial reconfiguration regions.
+        Modification of CSG software to support the extended \xilinx template.
     \itemL{18}{30}{x}{\Stima}{dynamic reconfiguration \ganttlf DNA drivers}{0:2:3}
         \setMacroInAuxFile{hpcDynconfDriver}
-        The drivers required by the DNA OS in order to manage dynamic partial reconfiguration inside the SoC-FPGA.
+            The drivers required by the DNA OS in order to manage dynamic partial
+        reconfiguration inside the SoC-FPGA.
     \itemL{30}{36}{x}{\Supmc}{dynamic reconfiguration \ganttlf MUTEK drivers}{0:0:1}
         Port of the {\hpcDynconfDriver} drivers on the MUTEK OS.
     \itemL{24}{36}{x}{\Stima}{HPC profiler for \ganttlf dynamic reconfiguration}{0:0:6}
-Extension of the HPC partionning helper in order to integrate dynamic partial reconfiguration dedicated features
-(reconfiguration time of regions, variable number of coprocessors)
-\end{livrable}
+        Extension of the HPC partionning helper in order to integrate dynamic partial
+        reconfiguration dedicated features (reconfiguration time of regions, variable
+        number of coprocessors).
+    \end{livrable}
 \item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board
     with its PCI/X IP. These boards are dedicated to the COACH HPC development.