source: anr/task-csg.tex @ 313

\begin{taskinfo}
\let\UPMC\leader
\let\TIMA\enable
\end{taskinfo}
%
\begin{objectif}
The objectives of this task are to allow the system designer to explore the
design space by quickly prototyping and then to automatically generate the
FPGA-SoC systems.  It is described on figure~\ref{archi-csg} and it consists of:
\begin{itemize}
  \item The development of the synthesizable models required for the connection
    of the coprocessors on the platform bus (2 bridges).
  \item The configuration and the development of drivers of the operating
    systems (Board Support Package, HAL).
  \item The CSG software that generates the SystemC simulators for prototyping
    and the FPGA-SoC system including its bitstream and software executable code
    (see Figure~\ref{archi-csg} and ~\ref{archi-hls}).
\end{itemize}
A first release will be delivered at $T0+12$ to allow the demonstrators to start working.
This release will include the standard communication schemes based on SoCLib MWMR component
and support the neutral architectural template for prototyping and hardware generation.
\end{objectif}
%
\begin{workpackage}
\subtask{Bridge implementation}
    This \ST deals with the development of the synthesizable models required for
    the connection of the coprocessors on the platform bus.
    \begin{livrable}
    \itemL{18}{30}{h}{\Stima}{HPC hardware \xilinx}{0:3:3}
        \setMacroInAuxFile{hpcPlbBridge}
        The synthesizable VHDL description of a VCI/\xilinxbus bridge.
    \itemL{18}{30}{h}{\Supmc}{HPC hardware \altera}{0:3:3}
        \setMacroInAuxFile{hpcAvalonBridge}
        The synthesizable VHDL description of an VCI/AVALON bridge.
    \end{livrable}
\subtask{OS setup}
    This \ST consists of the configuration of the SocLib DNA operating
    system and the development of drivers for the hardware architectural templates.
    For the \altera and \xilinx architectural templates, the OS must also be ported on
    the NIOS2 and \xilinxcpu processors.
    \begin{livrable}
    \itemV{6}{8}{x}{\Stima}{DNA OS}
        The drivers required for the first CSG milestone.
    \itemV{8}{18}{x}{\Stima}{DNA 0S}
        The drivers required for the second CSG milestone.
    \itemL{18}{33}{x}{\Stima}{DNA OS drivers for SoCLib}{6:2:2}
        \OtherPartner{6}{33}{\Supmc}  {.5:.5:.5}
        \mustbecompleted{TIMA : ajouter des précisions sur le travail et ce
        que fait upmc}
        Final release of the DNA OS drivers.
    \itemL{12}{18}{x}{\Stima}{Driver ports}{0:2:0}
        \OtherPartner{6}{33}{\Supmc}  {0:2:0}
    \mustbecompleted{TIMA: tima sur \xilinxcpu, UPMC sur Nios}
        Porting of DNA OS on the NIOS2 and \xilinxcpu processors.
    \end{livrable}
\subtask{Implementation of CSG}
    \begin{livrable}
    \itemV{0}{12}{x}{\Supmc}{CSG}
        The first software release of the CSG tool that will allow demonstrators to start
        working by using the neutral architectural template only for SystemC.
    \itemV{12}{18}{x}{\Supmc}{CSG}
        The second release of CSG integrates the VHDL driver for the neutral
        architectural template, and an integration of an HLS tools
        but only for SystemC prototyping.
    \itemV{18}{27}{x}{\Supmc}{CSG}
        This release extends CSG to FPGA-SoC generation for the \xilinx and
        \altera architectural template.
    \itemL{27}{36}{x}{\Supmc}{CSG tool}{5:2:3}
        \OtherPartner{0}{36}{\Stima}{1:3:2}
        \OtherPartner{0}{36}{\Smds}{1:3:3}
        \setMacroInAuxFile{csgImplementation}
        Final release of CSG enhanced by the demonstrator's feedback.
        \\
        The work will be split between the partner as follow: 1) \Supmc will
        design the core of CSG, 2) \Stima will design the part concerning the
        generation of system software and the configuration of CSG to other OS.
        3) \Smds will focus to interface CSG to the IP-XACT format for
        generating IP integrable into a IP-XACT flow such as socket and to
        configure CSG to new IP or plate-form.
    \end{livrable}
\end{workpackage}