Changeset 304 for anr/task-csg.tex

Timestamp:

Dec 23, 2010, 11:53:37 AM (14 years ago)

Author:

coach

Message:

MAJ des donnees LIP6 (quasi la derniere)

File:

• anr/task-csg.tex (modified) (3 diffs)

anr/task-csg.tex

@@ -10 +10 @@
 \begin{itemize}
   \item The development of the synthesizable models required for the connection
-        of the coprocessors on the platform bus (2 bridges).
+    of the coprocessors on the platform bus (2 bridges).
   \item The configuration and the development of drivers of the operating
-        systems (Board Support Package, HAL).
+    systems (Board Support Package, HAL).
   \item The CSG software that generates the SystemC simulators for prototyping
-        and the FPGA-SoC system including its bitstream and software executable code.
+    and the FPGA-SoC system including its bitstream and software executable code
+    (see Figure~\ref{architecture-csg} and ~\ref{architecture-hls}).
 \end{itemize}
 A first release will be delivered at $T0+12$ to allow the demonstrators to start working.
@@ -24 +25 @@
 \subtask{Bridge implementation}
     This \ST deals with the development of the synthesizable models required for
-        the connection of the coprocessors on the platform bus.
+    the connection of the coprocessors on the platform bus.
     \begin{livrable}
-    \itemL{18}{30}{h}{\Stima}{HPC hardware \xilinx}{0:2:5}
+    \itemL{18}{30}{h}{\Stima}{HPC hardware \xilinx}{0:3:3}
         \setMacroInAuxFile{hpcPlbBridge}
         The synthesizable VHDL description of a PLB/VCI bridge.
-    \itemL{18}{30}{h}{\Supmc}{HPC hardware \altera}{0:2:5}
+    \itemL{18}{30}{h}{\Supmc}{HPC hardware \altera}{0:3:3}
         \setMacroInAuxFile{hpcAvalonBridge}
         The synthesizable VHDL description of an AVALON/VCI bridge.
     \end{livrable}
 \subtask{OS setup}
-        This \ST consists of the configuration of the SocLib DNA operating
+    This \ST consists of the configuration of the SocLib DNA operating
     system and the development of drivers for the hardware architectural templates.
     For the \altera and \xilinx architectural templates, the OS must also be ported on
@@ -62 +63 @@
         architectural template, and an integration of an HLS tools
         but only for SystemC prototyping.
-    \itemV{18}{24}{x}{\Supmc}{CSG}
+    \itemV{18}{27}{x}{\Supmc}{CSG}
         This release extends CSG to FPGA-SoC generation for the \xilinx and
-                \altera architectural template.
-    \itemL{24}{36}{x}{\Supmc}{CSG tool}{5:3:2}
-        \OtherPartner{0}{36}{\Stima}{0:6:0}
-        \OtherPartner{0}{36}{\Smds}{0:6:0}
-                \setMacroInAuxFile{csgImplementation}
-        \mustbecompleted{TIMA : integration d'OS dans CSG, en particulier DNA}
+        \altera architectural template.
+    \itemL{27}{36}{x}{\Supmc}{CSG tool}{5:2:3}
+        \OtherPartner{0}{36}{\Stima}{1:3:2}
+        \OtherPartner{0}{36}{\Smds}{1:3:3}
+        \setMacroInAuxFile{csgImplementation}
         Final release of CSG enhanced by the demonstrator's feedback.
+        \\
+        The work will be split between the partner as follow: 1) \Supmc will
+        design the core of CSG, 2) \Stima will design the part concerning the
+        generation of system software and the configuration of CSG to other OS.
+        3) \Smds will focus to interface CSG to the IP-XACT format for
+        generating IP integrable into a IP-XACT flow such as socket and to
+        configure CSG to new IP or plate-form.
     \end{livrable}
 \end{workpackage}