1 | % vim:set spell: |
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2 | % vim:spell spelllang=en: |
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3 | |
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4 | \begin{taskinfo} |
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5 | \let\BULL\leader |
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6 | \let\UPMC\enable |
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7 | \let\TIMA\enable |
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8 | \let\XILINX\enable |
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9 | \end{taskinfo} |
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10 | % |
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11 | \begin{objectif} |
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12 | This task deals with the COACH HPC feature that consists in accelerating an existing |
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13 | application running on a PC by migrating critical parts into a SoC implemented on an |
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14 | FPGA plugged to the PC PCI/X bus (figures~\ref{coach-flow} and \ref{archi-hpc}). |
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15 | It consists in: |
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16 | \begin{itemize} |
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17 | \item Specifying and implementing the communication schemes between the software |
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18 | part running on the PC and the FPGA-SoC. |
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19 | \item Providing a performance analysis tool helping user in the HPC partitioning |
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20 | (figure~\ref{archi-hpc}). |
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21 | \item Providing support for configuration of the FPGA in order to set up the HPC environment. |
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22 | \end{itemize} |
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23 | The low level hardware transmission support will be the PCI/X bus which allows high bit-rate |
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24 | transfers. The reasons of this choice are that both \altera and \xilinx provide PCI/X IP for |
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25 | their FPGA and that GPU HPC softwares use also it. |
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26 | %This will allow us at least to be inspired by GPU communication schemes and may be to reuse |
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27 | %parts of the GPU softwares. |
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28 | \end{objectif} |
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29 | % |
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30 | \begin{workpackage} |
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31 | \subtask{Implementation of API between PC and FPGA-SoC} |
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32 | \begin{livrable} |
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33 | \itemL{0}{6}{d}{\Sbull}{HPC communication API}{3:0:0} |
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34 | \OtherPartner{0}{6}{\Supmc}{.5:0:0} |
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35 | \OtherPartner{0}{6}{\Stima}{.5:0:0} |
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36 | \setMacroInAuxFile{hpcCommApi} |
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37 | Specification of the API. |
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38 | \itemL{6}{12}{x}{\Supmc}{HPC partitioning helper}{1:0:0} |
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39 | \setMacroInAuxFile{hpcCommHelper} |
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40 | A library implementing the communication API defined in the {\hpcCommApi} deliverable. |
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41 | This library is dedicated to help the end-user to partition an application for HPC. |
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42 | \itemL{21}{27}{x}{\Stima}{HPC API for Linux}{0:2:1.5} |
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43 | \OtherPartner{21}{27}{\Supmc}{0:1.5:1.0} |
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44 | \OtherPartner{21}{27}{\Sbull}{0:0.5:0.5} |
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45 | \setMacroInAuxFile{hpcForLinux} |
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46 | This deliverable groups all the software components to implement the |
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47 | HPC communication API (\NOVERShpcCommApi). |
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48 | \Supmc will develop the Linux part (a C library and a LINUX module), |
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49 | \Stima will develop the FPGA-SoC part (a DNA driver), |
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50 | \Sbull will check this implementation on its demonstrator (\NOVERSbullAppSpecification). |
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51 | \end{livrable} |
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52 | % |
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53 | \subtask{SystemC model of the PCI/X} |
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54 | This \ST deals with the implementation of SystemC modules |
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55 | required by the neutral architectural template for using the PCI/X IP of \altera and \xilinx. |
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56 | \begin{livrable} |
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57 | \itemL{21}{27}{h}{\Supmc}{PCI/X traffic generator}{0:1:1} |
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58 | The SystemC description of a component that generates PCI/X traffic. It is |
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59 | required to prototype FPGA-SoC dedicated to HPC. |
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60 | \end{livrable} |
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61 | % |
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62 | \subtask{HPC environment set up} |
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63 | % It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library. |
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64 | \begin{livrable} |
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65 | \itemL{18}{36}{x}{\Stima}{Support for HPC \ganttlf environment set up}{0:3:3} |
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66 | Modification of the CSG software to set-up the HPC environment. |
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67 | The objective is to run easily HPC application and the main features are: |
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68 | automatic calibration of coprocessors (\freqCalibrationVhdl), automatic download of |
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69 | SoC on FPGA (bitstream and application loader), starting the PC and FPGA |
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70 | part of the HPC application. |
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71 | \end{livrable} |
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72 | % |
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73 | \end{workpackage} |
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