Changeset 356 for anr/task-hpc.tex

Timestamp:

Feb 6, 2011, 2:29:09 PM (13 years ago)

Author:

coach

Message:

1ere Pre-release

File:

• anr/task-hpc.tex (modified) (4 diffs)

anr/task-hpc.tex

@@ -6 +6 @@
 \let\UPMC\enable
 \let\TIMA\enable
-\let\THALES\enable
 \let\XILINX\enable
 \end{taskinfo}
@@ -43 +42 @@
       \itemL{21}{27}{x}{\Stima}{HPC API for Linux}{0:2:1.5}
         \OtherPartner{21}{27}{\Supmc}{0:1.5:1.0}
-        \OtherPartner{21}{27}{\Sbull}{0:0.0:0.5}
+        \OtherPartner{21}{27}{\Sbull}{0:0.5:0.5}
         \setMacroInAuxFile{hpcForLinux}
         This deliverable groups all the software components to implement the
@@ -64 +63 @@
 % It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library.
      \begin{livrable}
-     \itemL{18}{36}{x}{\Stima}{Support for HPC environment set up}{0:3:3}
+     \itemL{18}{36}{x}{\Stima}{Support for HPC \ganttlf environment set up}{0:3:3}
       Modification of the CSG software to set-up the HPC environment.
       The objective is to run easily HPC application and the main features are:
@@ -71 +70 @@
       part of the HPC application.
      \end{livrable}
-%     \itemL{18}{36}{x}{\Stima}{CSG module for \ganttlf dynamic reconfiguration}{0:4:12}
-%       This livrable is a CSG module allowing to partition the task graph along
-%       the dynamic partial reconfiguration regions. The resulting task-region assignement
-%       is directly used for generation of bitstreams. The module also produces reconfiguration
-%       management software to be run on the SoC-FPGA.
-%     \itemL{18}{30}{x}{\Stima}{Dynamic reconfiguration \ganttlf for DNA drivers}{0:3:3}
-%         \setMacroInAuxFile{hpcDynconfDriver}
-%       The drivers required by the DNA OS in order to manage dynamic partial
-%         reconfiguration inside the SoC-FPGA.
-%     \itemL{30}{36}{x}{\Supmc}{Dynamic reconfiguration \ganttlf for  MUTEKH drivers}{0:0:1}
-%         Port of the {\hpcDynconfDriver} drivers on the MUTEKH OS.
-%     \itemL{24}{36}{x}{\Stima}{Profiler for \ganttlf dynamic reconfiguration}{0:0:6}
-%         Extension of the HPC partionning helper in order to integrate dynamic partial
-%         reconfiguration dedicated features (reconfiguration time of regions, variable
-%         number of coprocessors).
-%     \itemL{24}{36}{d}{\Sxilinx}{Optimisation for \xilinx \ganttlf dynamic reconfiguration}{0:0:2}
-%         \xilinx will work with \tima in order to better take into account during
-%         partitioning decisions specific constraints due to partial reconfiguration process.
-%         The deliverable is a document describing the \xilinx specific constraints.
-%     \end{livrable}
-% %\item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board
-% %   with its PCI/X IP. These boards are dedicated to the COACH HPC development.
-% %   They are based on \mustbecompleted{FIXME:stratix4} FPGA device of 400,000 LUT.
-% %   \begin{livrable}
-% %   \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards.
+%
 \end{workpackage}