Changeset 102 for anr

Timestamp:

Feb 8, 2010, 8:40:36 AM (15 years ago)

Author:

coach

Message:

pc

File:

• anr/section-2.2.tex (modified) (1 diff)

anr/section-2.2.tex

@@ -7 +7 @@
 The COACH project answers to several of the challenges found in different axis of the call for proposals. Keywords of the call are indicated below in italic writing.
 
-Axis 1 « Architectures des systÚmes embarques » :
+Axis 1 "Architectures des systemes embarque" :
 
 COACH will address new embedded systems architectures by allowing the design of  Multi-Core Systems-on-Chip (possibly heterogeneous) on FPGA according to the design constraints and objectives (real-time, low-power). It will permit to design  complex SoC  based on IP cores ((memory, peripherals, network controllers, communication processors), running Embedded Software, as well as an Operating System with associated middleware and API and using hardware accelerator automatically generated. It will also permit to use efficiently different dynamic system management techniques and re-configuration mechanisms. 
 
-Axis 2 « Infrastructures pour l'Internet, le calcul intensif ou les services » :
+Axis 2 "Infrastructures pour l'Internet, le calcul intensif ou les services" :
 
 COACH will address High-Performance Computing (HPC) by helping designer to accelerate an application running on a PC by migrating critical parts into a SoC implemented on an FPGA plugged to the PC bus (through a communication link like PCI/X). COACH will reduce the designer effort through the development of tools that translate high level language programs to FPGA configurations. Moreover, Dynamic Partial Reconfiguration will be used for improving HPC performance as well as reducing the required area.
 
-Axis 3 « Robotique et contrÎle/commande » :
+Axis 3 "Robotique et controle/commande" :
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