Changeset 103 for anr

Timestamp:

Feb 8, 2010, 8:59:54 AM (15 years ago)

Author:

coach

Message:

pc

File:

• anr/section-3.1.tex (modified) (5 diffs)

anr/section-3.1.tex

@@ -51 +51 @@
 \subsubsection{System Synthesis}
 Today, several solutions for system design are proposed and commercialized.
-The most common are those provided by Altera and Xilinx to promote their
-FPGA devices.
+The existing commercial or free tools does not
+cover the whole system synthesis process in a full automatic way. Moreover,
+they are bound to a particular device family and to IPs library.
+The most commonly used are provided by Altera and Xilinx to promote their
+FPGA devices. These two representative tools used to synthesize SoC on FPGA
+are introduced below.
 \\
 The Xilinx System Generator for DSP~\cite{system-generateur-for-dsp} is a
@@ -61 +65 @@
 Language (HDL) code mapped to Xilinx pre-optimized algorithms.
 However, this tool targets only DSP based algorithms, Xilinx FPGAs and
-cannot handle complete SoC. Thus, it is not really a system synthesis tool.
+cannot handle a complete SoC. Thus, it is not really a system synthesis tool.
 \\
 In the opposite, SOPC Builder~\cite{spoc-builder} allows to describe a
@@ -69 +73 @@
 Nevertheless, SOPC Builder does not provide any facilities to synthesize
 coprocessors. System Designer must provide the synthesizable description
-with the feasible bus interface.
+with the feasible bus interface. Design Space Exploration is thus limited
+and SystemC simulation is not possible neither at transactional nor at Cycle
+accurate level. 
 \\
 In addition, Xilinx System Generator and SOPC Builder are closed world
 since each one imposes their own IPs which are not interchangeable.
-The existing commercial or free tools does not
-cover the whole system synthesis process in a full automatic way. Moreover,
-they are bound to a particular device family and to IPs library.
 
 \subsubsection{High Level Synthesis}
@@ -87 +90 @@
 maturity, their usage is restrained by:
 \begin{itemize}
-\item They do not respect accurately the frequency constraint when they target an FPGA device.
-Their error is about 10 percent. This is annoying when the generated component is integrated
-in a SoC since it will slow down the hole system.
-\item These tools take into account only one or few constraints simultaneously while realistic
-designs are multi-constrained. 
-Moreover, low power consumption constraint is mandatory for embedded systems. 
-However, it is not yet well handled by common synthesis tools.
-\item The parallelism is extracted from initial algorithm. To get more parallelism or to reduce
-the amout of required memory, the user must re-write it while there is techniques as polyedric 
-transformations to increase the intrinsec parallelism.
-\item Despite they have the same input language (C/C++), they are sensitive to the style in
-which the algorithm is written. Consequently, engineering work is required to swap from 
-a tool to another.
 \item The HLS tools are not integrated into an architecture and system exploration tool.
 Thus, a designer who needs to accelerate a software part of the system, must adapt it manually 
 to the HLS input dialect and performs engineering work to exploit the synthesis result 
 at the system level.
+\item HLS tools take into account only one or few constraints simultaneously while realistic
+designs are multi-constrained. 
+Moreover, low power consumption constraint is mandatory for embedded systems. 
+However, it is not yet well handled or not handle at all by the synthesis tools already available.
+\item The parallelism is extracted from initial algorithmic specification. To get more parallelism or to reduce
+the amount of required memory in the SoC, the user must re-write the algorithmic specification while there is 
+techniques as polyedric transformations to increase the intrinsic parallelism.
+\item While they support limited loop transformations like loop unrolling and loop pipelining, current HLS tools 
+do not provide support for design space exploration neither through automatic loop transformations nor through 
+memory mapping. 
+\item Despite they have the same input language (C/C++), they are sensitive to the style in
+which the algorithm is written. Consequently, engineering work is required to swap from 
+a tool to another.
+\item They do not respect accurately the frequency constraint when they target an FPGA device.
+Their error is about 10 percent. This is annoying when the generated component is integrated
+in a SoC since it will slow down the hole system.
 \end{itemize}
 Regarding these limitations, it is necessary to create a new tool generation reducing the gap 
-between the specification of an heterogenous system and its hardware implementation.
+between the specification of an heterogeneous system and its hardware implementation.
+%FIXME == {Ajouter ref livre + D&T}
 
 \subsubsection{Application Specific Instruction Processors}
@@ -112 +119 @@
 ASIP (Application-Specific Instruction-Set Processor) are programmable
 processors in which both the instruction and the micro architecture have
-been tailored to a given application domain (eg. video processing), or to a
+been tailored to a given application domain (e.g. video processing), or to a
 specific application.  This specialization usually offers a good compromise
-between performance (w.r.t a pure software implementation on an embeded
+between performance (w.r.t a pure software implementation on an embedded
 CPU) and flexibility (w.r.t an application specific hardware co-processor).
 In spite of their obvious advantages, using/designing ASIPs remains a