Changeset 120 for anr/section-2.2.tex

Timestamp:

Feb 9, 2010, 2:12:33 PM (14 years ago)

Author:

coach

Message:

FC : Mise à jour de la partie IRISA qui devient maintenant INRIA

IRISA est changé en INRIA/CAIRN
LIP est changé en INRIA/COMPSYS

File:

• anr/section-2.2.tex (modified) (2 diffs)

anr/section-2.2.tex

@@ -68 +68 @@
     this project enhances SoCLib by providing the synthesisable VHDL models required
     for FPGA synthesis.
-  \item[ROMA]
-    The ROMA ANR project (2007-2009) involving IRISA, LIRMM, CEA List THOMSON France R\&D, proposes to develop a
-    reconfigurable processor, exhibiting high silicon density and power efficiency, able to adapt its
-    computing structure to computation patterns that can be speed-up and/or power efficient. 
-    The ROMA project study a pipeline-based of evolved low-power coarse grain reconfigurable
-    operators to avoid traditional overhead, in reconfigurable devices, related to 
-    the interconnection network. 
-    The project will borrow from the ROMA ANR xxproject (2007-2009) and the ongoing 
-    joint INRIA-STMicro Nano2012 project to adapt existing pattern
-    extraction algorithms and datapath merging techniques to the synthesis of customized 
+  \item[ROMA] The ROMA ANR project (http://roma.irisa.fr, 2007-2010)
+    involving IRISA (CAIRN team), LIRMM, CEA List THOMSON France R\&D,
+    proposes to develop a reconfigurable processor, exhibiting high
+    silicon density and power efficiency, able to adapt its computing
+    structure to computation patterns that can be speed-up and/or
+    power efficient.  The ROMA project study a pipeline-based of
+    evolved low-power coarse grain reconfigurable operators to avoid
+    traditional overhead, in reconfigurable devices, related to the
+    interconnection network.  The project will borrow from the ROMA
+    ANR project and the ongoing joint INRIA-STMicro
+    Nano2012 project to adapt existing pattern extraction algorithms
+    and datapath merging techniques to the synthesis of customized
     ASIP processors.
   \item[TSAR]
@@ -108 +110 @@
   \item
     Regarding Application Specific Instruction Processor (ASIP) design, the
-    CAIRN group at INRIA Bretagne Atlantique benefits from several years of
+    CAIRN group at INRIA Rennes -- Bretagne Atlantique benefits from several years of
     expertise in the domain of retargetable compiler
     (Armor/Calife~\cite{CODES99} since 1996, and the Gecos