Changeset 134 for anr/section-3.1.tex

Timestamp:

Feb 13, 2010, 3:24:29 PM (14 years ago)

Author:

coach

Message:

IA: fixed mutek, altera, xilinx, and neutal architectural template

File:

• anr/section-3.1.tex (modified) (4 diffs)

anr/section-3.1.tex

@@ -54 +54 @@
 cover the whole system synthesis process in a full automatic way. Moreover,
 they are bound to a particular device family and to IPs library.
-The most commonly used are provided by Altera and Xilinx to promote their
+The most commonly used are provided by \altera and \xilinx to promote their
 FPGA devices. These two representative tools used to synthesize SoC on FPGA
 are introduced below.
 \\
-The Xilinx System Generator for DSP~\cite{system-generateur-for-dsp} is a
+The \xilinx System Generator for DSP~\cite{system-generateur-for-dsp} is a
 plug-in to Simulink that enables designers to develop high-performance DSP
-systems for Xilinx FPGAs.
+systems for \xilinx FPGAs.
 Designers can design and simulate a system using MATLAB and Simulink. The
 tool will then automatically generate synthesizable Hardware Description
-Language (HDL) code mapped to Xilinx pre-optimized algorithms.
-However, this tool targets only DSP based algorithms, Xilinx FPGAs and
+Language (HDL) code mapped to \xilinx pre-optimized algorithms.
+However, this tool targets only DSP based algorithms, \xilinx FPGAs and
 cannot handle a complete SoC. Thus, it is not really a system synthesis tool.
 \\
@@ -70 +70 @@
 system, to synthesis it, to programm it into a target FPGA and to upload a
 software application.
-% FIXME(C2H from Altera, marche vite mais ressource monstrueuse)
+% FIXME(C2H from \altera, marche vite mais ressource monstrueuse)
 Nevertheless, SOPC Builder does not provide any facilities to synthesize
 coprocessors. System Designer must provide the synthesizable description
@@ -77 +77 @@
 accurate level. 
 \\
-In addition, Xilinx System Generator and SOPC Builder are closed world
+In addition, \xilinx System Generator and SOPC Builder are closed world
 since each one imposes their own IPs which are not interchangeable.
 
@@ -98 +98 @@
 Moreover, low power consumption constraint is mandatory for embedded systems. 
 However, it is not yet well handled or not handle at all by the synthesis tools already available.
-\item The parallelism is extracted from initial algorithmic specification. To get more parallelism or to reduce
-the amount of required memory in the SoC, the user must re-write the algorithmic specification while there is 
-techniques as polyedric transformations to increase the intrinsic parallelism.
-\item While they support limited loop transformations like loop unrolling and loop pipelining, current HLS tools 
-do not provide support for design space exploration neither through automatic loop transformations nor through 
-memory mapping. 
+\item The parallelism is extracted from initial algorithmic specification.
+To get more parallelism or to reduce the amount of required memory in the SoC, the user
+must re-write the algorithmic specification while there is techniques as polyedric
+transformations to increase the intrinsic parallelism.
+\item While they support limited loop transformations like loop unrolling and loop
+pipelining, current HLS tools do not provide support for design space exploration neither
+through automatic loop transformations nor through memory mapping.
 \item Despite they have the same input language (C/C++), they are sensitive to the style in
 which the algorithm is written. Consequently, engineering work is required to swap from