Changeset 136

Timestamp:

Feb 13, 2010, 9:41:56 PM (15 years ago)

Author:

coach

Message:

IA: added Indusrial Interest sub section

File:

• anr/section-5.tex (modified) (2 diffs)

anr/section-5.tex

@@ -48 +48 @@
 
 This general approach is supported by a large number of SMEs, as demonstrated by the "letters
-of interest" that have been collected during the preparation of the project :
+of interest" that have been collected during the preparation of the project and presented
+in annexe~\ref{lettre-soutien}.
+
+\subsection{Indusrial Interest in COACH}
+
+\subsubsection*{Partner: \textit{\bull}}
+The team of \bull participating to the COACH project is from the Server Development
+Department who is in charge of developing hardware for open servers (e.g. NovaScale) and
+HPC solutions. The main expectation from COACH is to derive a new component (fine-grain
+FPGA parallelism) to add to existing Bull HPC solutions.
+
+\subsubsection*{Partner: \textit{\xilinx}}
+Computing power potential of our FPGA architectures
+growing very quickly on one side, and complexity of designs implemented
+using our FPGAs dramatically increasing on the other side, it is very
+interesting for us to get high level design methodologies progressing
+quickly and targetting our FPGAs in the most possible efficient way.
+\parlf
+\xilinx goal is to get COACH to generate bitstream optimized as much as possible for
+\xilinx FPGAs in order to both, validate the methodology on our FPGA families, and ease
+future work of our customers.
+
+\subsubsection*{Partner: \textit{\thales}}
+\noindent
+\thales has two main reasons to use the COACH platform:
+\begin{itemize}
+  \item The huge increase of the complexity of the systems in particular by their
+  heterogeneity, raises the issues of design cost and time in the same proportion. The
+  divisions need a design tool which supports the implementation of the applications from
+  algorithm description to the executable code on platforms composed of several general
+  purpose processors and dedicated IPs.
+  \item The applications are more and more complex and adaptable to the environment which
+  leads to a mixture of control aspects and data stream computing aspects. A new approach
+  is necessary to be able to describe this type of application and manage the high level
+  synthesis of system embedding control and data flow aspects.
+\end{itemize}
+\parlf
+TRT (Thales Research and Technology) has the mission to assess and de-risk the emerging
+technologies in its domains of expertise. Specifically in COACH, the studied technology is
+a method and associated tools to make the bridge between application capture at system
+level and the implementation on heterogeneous distributed computing architectures. The
+main stake for Thales behind this is the future design process that will be applied to its
+system teams in the future for the computation-intensive sensor applications. In a context
+of very instable market of tools for parallel programming, it is important to experiment
+and demonstrate the candidate technologies.
+\\
+In its role of internal dissemination, TRT will make the demonstration of the full design
+flow within Thales, and will keep available a platform to later evaluate additional
+applications coming from the Business Units.
+\\
+The COACH platform will be used in the new \thales products in which the algorithms are more
+and more dependent of the environment and have to permanently adapt their behavior in
+varying environments. The target markets are the critical infrastructures security and
+border monitoring.
+
+\subsubsection*{Partner: \textit{\zied}}
+
+\zied is developing a new architecture for embedded system. Our interest in using COACH
+are:
+\begin{itemize}
+  \item firstly, to validate our new architecture by emulating it with COACH.
+  \item Secondly, to use this emulator and the COACH potential to quickly setup
+  demonstrator to our customer.
+\end{itemize}
+
+\subsubsection*{Partner: \textit{\navtel}}
+\navtel has a platform for high performence computation based on ARM processor and FPGAs
+that embedde coprocessors. Currently, the coprocessors are handmade and their designs
+constitute an important part of our product cost. We have try free HLS tools to diminish
+them but the quality of the generated designs was not sufficient to be useable.
+So our interest in COACH is mainly the HLS tools.
+
+\subsubsection*{Industrial supports}
+The following SMEs demonstrate interest to the COACH project (see the "letters of
+interest" in annexe~\ref{lettre-soutien}) and will follow the COACH evolution and will
+evaluate it:
 \begin{itemize}
 \item \mustbecompleted{Entreprise 1}
@@ -57 +132 @@
 
 \subsection{Management of Intellectual Property}
-
 A global consortium agreement will be defined during the first six monts of the project.
 As already stated, the COACH project has been prepared during one year by a monthly meeting