Changeset 165 for anr/section-1.tex


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Timestamp:
Feb 15, 2010, 11:45:28 AM (15 years ago)
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coach
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UBS

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  • anr/section-1.tex

    r134 r165  
    55complex Multi-Processors System on Chip (MPSoC).
    66\\
     7\mustbecompleted{FIXME :: A relire, j'ai modifie le paragraphe suivant en motivant plus}
    78During the last decade, the design of ASICs (Application Specific
    89Integrated Circuits) appeared to be more and more reserved to high volume markets, because
     
    1213Virtex5 family from \xilinx or the Stratix4 family from \altera, can nowadays
    1314implement a complete MPSoC with multiple processors and several dedicated
    14 coprocessors for a few keuros per device.
    15 In addition, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
     15coprocessors for a few Keuros per device. Many applications are initially captured
     16algorithmically in High-Level Languages HLLs such as C/C++. This has led to growing interest
     17in tools that can provide an implementation path directly from HLLs to hardware.
     18Thus, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
    1619Co-design, High-Level Synthesis...) are now mature and allow the automation of
    17 a system level design flow that targets FPGA devices.
     20a system-level design flow. Unfortunately, ESL tool development to date has primarily focused
     21on the design of hard-wired devices i.e. ASICs and ASSPs (Application Specific Standard Product).
     22However, the increasing sophistication of FPGAs has accelerated the need for FPGA-based ESL design
     23methodologies. ESL methodologies hold the promise of streamlining the design approach by accepting
     24designs written in C/C++ language and implementing the function straight into FPGA.
    1825We believe that coupling FPGA technologies and ESL methodologies
    1926will allow both SMEs (Small and Medium Enterprise) and
     
    2835They can be embedded (autonomous) applications
    2936such as personal digital assistants (PDA), ambiant computing components,
    30 or wireless sensor networks (WSN)
     37or wireless sensor networks (WSN).
    3138They can also be extension boards connected to a PC to accelerate a specific computation,
    3239as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP).
     
    5764    COACH will define architectural templates that can be customized by adding
    5865    dedicated coprocessors and ASIPs and by fixing template parameters such as
    59     the number of embedded processors or the number of sizes of embedde memory banks,
     66    the number of embedded processors, the number of sizes of embedded memory banks
    6067    or the embedded the operating system.
     68    However, the specification of the application will be independant of both the
     69    architectural template and the target FPGA device.
    6170    Basically, the 3 following architectural templates will be provided:
    6271    \begin{enumerate}
    63     \item A Neutral architectural template based on the SoCLib IP core library and the
     72    \item A \mustbecompleted{FIXME :: Neutral est tres pejoratif. Technology inependent, independant, standard ???} Neutral architectural template based on the SoCLib IP core library and the
    6473      VCI/OCP communication infrastructure.
    65     \item An \altera architectural template based on the \altera IP core library and the
    66       AVALON system bus.
    67     \item A \xilinx architectural template based on the Xlinx IP core library and the PLB
    68       system bus.
     74    \item An \altera architectural template based on the \altera IP core library, the
     75      AVALON system bus and the NIOS processor.
     76    \item A \xilinx architectural template based on the Xilinx IP core library, the PLB
     77      system bus and the Microblaze processor.
    6978    \end{enumerate}
    70     Moreover, the specification of the application will be independant of both the
    71     architectural template and the target FPGA device.
    7279\item[Hardware/Software communication middleware:]
    7380    COACH will implement an homogeneous HW/SW communication infrastructure and
    7481    communication APIs (Application Programming Interface), that will be used for
    7582    communications between software tasks running on embedded processors and
    76     dedicated hardware coprocessors,
     83    dedicated hardware coprocessors.
    7784\end{description}
    7885The COACH design flow will be dedicated to system designers, and will as
    79 much as possible hide the hardware characteristics to the end user.
     86much as possible hide the hardware characteristics to the end-user.
    8087%From the end user point of view, the specification of the application will be
    8188%independant from both the architectural template and from the selected FPGA
     
    95102\\
    96103The COACH project does not start from scratch.
    97 It stronly relies on SoCLib virtual prototyping platform~\cite{soclib} for prototyping,
     104It stronly relies on the SoCLib virtual prototyping platform~\cite{soclib} for prototyping,
    98105
    99106(DSX, component library), operating systems (MUTEKH, DNA/OS).
     
    103110on the SYNTOL~\cite{syntol} and BEE~\cite{bee} tools for source-level analysis and transformations
    104111and on the \xilinx and \altera IP core libraries.
    105 Finally it will use the \xilinx and \altera RTL tools to generate the FPGA configuration
     112Finally it will use the \xilinx and \altera logic and phisical synthesis tools to generate the FPGA configuration
    106113bitstreams.
    107114\parlf
     
    112119Most of the general software architecture of the proposed design flow (including the
    113120exchange format specification) has been define by this working group.
    114 Because the SocLib platform is the base of this project, it may be described as an
     121Because the SoCLib platform is the \mustbecompleted{FIXME Fundation, root, basis ???} base of this project, it may be described as an
    115122extension of the SoCLib platform.
    116123%The main development steps of the COACH project are:
     
    137144as a contractual partner providing documentation and manpower; \altera will contribute as a supporter,
    138145providing documentation and development boards. These two companies are strongly motivated
    139 to help the COACH project to generate efficient bitsream for both FPGA families.
     146to help the COACH project to generate efficient bitsreams for both FPGA families.
    140147The role of the industrial partners \bull, \thales, \navtel and \zied is to provide
    141 real use cases to benchmark the COACH design environment.
     148real use cases to benchmark the COACH design environment and to analyze the designer productivity
     149imrovments. \mustbecompleted{FIXME :: j'ai ajoute and to analyze OK ?...} \mustbecompleted{FIXME :: FlexRAS
     150sont fournisseur de techno et non de uses cases no ???}
    142151\parlf
    143152Following the general policy of the SoCLib platform, the COACH project will be an open
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