Changeset 171
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- Feb 15, 2010, 2:15:35 PM (15 years ago)
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anr/section-2.1.tex
r134 r171 18 18 \end{table} 19 19 % 20 Microelectronic components allow the integration of compl icatedfunctions into products, increases20 Microelectronic components allow the integration of complex functions into products, increases 21 21 commercial attractivity of these products and improves their competitivity. 22 22 Multimedia and tele-communication sectors have taken advantage from microelectronics facilities 23 23 thanks to the developpment of design methodologies and tools for embedded systems. 24 Unfortunately, the Non Recurring Engineering (NRE) costs involded in designing24 Unfortunately, the Non Recurring Engineering (NRE) costs involded in the design 25 25 and manufacturing ASICs is very high. 26 26 An IC foundry costs several billions of euros and the fabrication of a specific circuit 27 27 costs several millions. For example a conservative estimate for a 65nm ASIC project is 10 28 28 million USD. 29 Consequently, it is generally unfeasible to design and fabricate ASICs for low and medium29 Consequently, it is more and more unaffordable to design and fabricate ASICs for low and medium 30 30 volume markets. 31 31 \parlf … … 35 35 microprocessors implementation. There is still a performance degradation of one order 36 36 of magnitude versus an equivalent ASIC implementations, but low cost 37 (500 euros to 10K euros), fast time tomarket and flexibility of FPGAs make them an attractive37 (500 euros to 10K euros), fast time-to-market and flexibility of FPGAs make them an attractive 38 38 choice for low-to-medium volume applications. 39 39 Since their introduction in the mid eighties, FPGAs evolved from a simple, … … 61 61 \parlf 62 62 This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion 63 of FPGA-based solutions is limited by the lack of design flowautomation.63 of FPGA-based solutions is limited by the lack of design automation. 64 64 Nowadays, there are neither commercial nor academic tools covering the whole design process 65 65 from the system level specification to the bit stream generation. 66 \\67 66 % IA to Alain: J'ai remis (et ameliore un peu) ca car sinon le Consequently 20 lignes 68 67 % au dessous n'a pas de sens. 69 68 % Deplus dans les demandes ANR de la section, il est demande: analyse de la concurrence 70 For instance, withSOPC Builder~\cite{spoc-builder} from \altera, designers can select and69 By using SOPC Builder~\cite{spoc-builder} from \altera, designers can select and 71 70 parameterize components from an extensive drop-down list of IP cores (I/O core, DSP, 72 71 processor, bus core, ...) as well as incorporate their own IP. … … 79 78 In addition, SOPC Builder is proprietary and only works together with \altera's Quartus compilation 80 79 tool to implement designs on \altera devices (Stratix, Arria, Cyclone). 81 \\ 82 For instance, PICO~\cite{pico} and CATAPULT-C~\cite{catapult-c} allow to synthesize 80 PICO~\cite{pico} and CATAPULT-C~\cite{catapult-c} allow to synthesize 83 81 coprocessors from a C++ description. 84 82 Nevertheless, they can only deal with data dominated applications and they do not handle 85 83 the platform level. 86 \\87 84 Similarly, the System Generator for DSP~\cite{system-generateur-for-dsp} is a plug-in to 88 85 Simulink that enables designers to develop high-performance DSP systems for \xilinx FPGAs. … … 95 92 design environments: 96 93 \begin{enumerate} 97 \item a virtual prototyping environment such as SoCLibfor system level exploration,94 \item a virtual prototyping environment for system level exploration, 98 95 \item an architecture compiler (such as SOPC Builder from \altera, or System generator 99 96 from \xilinx) to define the hardware architecture, … … 105 102 the design process very complex and achievable only by designers skilled in many domains. 106 103 \begin{center}\begin{minipage}{.8\linewidth}\textit{ 107 The aim of the COACH project is to integrate all these design steps into a single design framework .104 The aim of the COACH project is to integrate all these design steps into a single design framework 108 105 and to allow \textbf{pure software} developpers to develop embedded systems. 109 106 }\end{minipage}\end{center} 110 107 \parlf 111 108 We believe that the combination of a design environment dedicated to software developpers 112 and the FPGA target,113 allowssmall and even very small companies to propose embedded system and accelerating solutions114 for standard software applications with a cceptable prices.109 and FPGA targets, 110 will allow small and even very small companies to propose embedded system and accelerating solutions 111 for standard software applications with attractive and competitive prices. 115 112 This new market may explode in the same way as the micro-computer market in the eighties, 116 113 whose success was due to the low cost of the first micro-processors (compared to main frames)
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