Changeset 171


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Timestamp:
Feb 15, 2010, 2:15:35 PM (15 years ago)
Author:
coach
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UBS

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  • anr/section-2.1.tex

    r134 r171  
    1818\end{table}
    1919%
    20 Microelectronic components allow the integration of complicated functions into products, increases
     20Microelectronic components allow the integration of complex functions into products, increases
    2121commercial attractivity of these products and improves their competitivity.
    2222Multimedia and tele-communication sectors have taken advantage from microelectronics facilities
    2323thanks to the developpment of design methodologies and tools for embedded systems.
    24 Unfortunately, the Non Recurring Engineering (NRE) costs involded in designing
     24Unfortunately, the Non Recurring Engineering (NRE) costs involded in the design
    2525and manufacturing ASICs is very high.
    2626An IC foundry costs several billions of euros and the fabrication of a specific circuit
    2727costs several millions. For example a conservative estimate for a 65nm ASIC project is 10
    2828million USD.
    29 Consequently, it is generally unfeasible to design and fabricate ASICs for low and medium
     29Consequently, it is more and more unaffordable to design and fabricate ASICs for low and medium
    3030volume markets.
    3131\parlf
     
    3535microprocessors implementation. There is still a performance degradation of one order
    3636of magnitude versus an equivalent ASIC implementations, but low cost
    37 (500 euros to 10K euros), fast time to market and flexibility of FPGAs make them an attractive
     37(500 euros to 10K euros), fast time-to-market and flexibility of FPGAs make them an attractive
    3838choice for low-to-medium volume applications.
    3939Since their introduction in the mid eighties, FPGAs evolved from a simple,
     
    6161\parlf
    6262This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion
    63 of FPGA-based solutions is limited by the lack of design flow automation.
     63of FPGA-based solutions is limited by the lack of design automation.
    6464Nowadays, there are neither commercial nor academic tools covering the whole design process
    6565from the system level specification to the bit stream generation.
    66 \\
    6766% IA to Alain: J'ai remis (et ameliore un peu) ca car sinon le Consequently 20 lignes
    6867%              au dessous n'a pas de sens.
    6968% Deplus dans les demandes ANR de la section, il est demande: analyse de la concurrence
    70 For instance, with SOPC Builder~\cite{spoc-builder} from \altera, designers can select and
     69By using SOPC Builder~\cite{spoc-builder} from \altera, designers can select and
    7170parameterize components from an extensive drop-down list of IP cores (I/O core, DSP,
    7271processor,  bus core, ...) as well as incorporate their own IP.
     
    7978In addition, SOPC Builder is proprietary and only works together with \altera's Quartus compilation
    8079tool to implement designs on \altera devices (Stratix, Arria, Cyclone).
    81 \\
    82 For instance, PICO~\cite{pico} and CATAPULT-C~\cite{catapult-c} allow to synthesize
     80PICO~\cite{pico} and CATAPULT-C~\cite{catapult-c} allow to synthesize
    8381coprocessors from a C++ description.
    8482Nevertheless, they can only deal with data dominated applications and they do not handle
    8583the platform level.
    86 \\
    8784Similarly, the System Generator for DSP~\cite{system-generateur-for-dsp} is a plug-in to
    8885Simulink that enables designers to develop high-performance DSP systems for \xilinx FPGAs.
     
    9592design environments:
    9693\begin{enumerate}
    97   \item a virtual prototyping environment such as SoCLib for system level exploration,
     94  \item a virtual prototyping environment for system level exploration,
    9895  \item an architecture compiler (such as SOPC Builder from \altera, or System generator
    9996  from \xilinx) to define the hardware architecture,
     
    105102the design process very complex and achievable only by designers skilled in many domains.
    106103\begin{center}\begin{minipage}{.8\linewidth}\textit{
    107 The aim of the COACH project is to integrate all these design steps into a single design framework.
     104The aim of the COACH project is to integrate all these design steps into a single design framework
    108105and to allow \textbf{pure software} developpers to develop embedded systems.
    109106}\end{minipage}\end{center}
    110107\parlf
    111108We believe that the combination of a design environment dedicated to software developpers
    112 and the FPGA target,
    113 allows small and even very small companies to propose embedded system and accelerating solutions
    114 for standard software applications with acceptable prices.
     109and FPGA targets,
     110will allow small and even very small companies to propose embedded system and accelerating solutions
     111for standard software applications with attractive and competitive prices.
    115112This new market may explode in the same way as the micro-computer market in the eighties,
    116113whose success was due to the low cost of the first micro-processors (compared to main frames)
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