Changeset 171 for anr/section-2.1.tex

Timestamp:

Feb 15, 2010, 2:15:35 PM (14 years ago)

Author:

coach

Message:

UBS

File:

• anr/section-2.1.tex (modified) (6 diffs)

anr/section-2.1.tex

@@ -18 +18 @@
 \end{table}
 %
-Microelectronic components allow the integration of complicated functions into products, increases
+Microelectronic components allow the integration of complex functions into products, increases
 commercial attractivity of these products and improves their competitivity.
 Multimedia and tele-communication sectors have taken advantage from microelectronics facilities
 thanks to the developpment of design methodologies and tools for embedded systems.
-Unfortunately, the Non Recurring Engineering (NRE) costs involded in designing
+Unfortunately, the Non Recurring Engineering (NRE) costs involded in the design
 and manufacturing ASICs is very high.
 An IC foundry costs several billions of euros and the fabrication of a specific circuit
 costs several millions. For example a conservative estimate for a 65nm ASIC project is 10
 million USD.
-Consequently, it is generally unfeasible to design and fabricate ASICs for low and medium
+Consequently, it is more and more unaffordable to design and fabricate ASICs for low and medium
 volume markets.
 \parlf
@@ -35 +35 @@
 microprocessors implementation. There is still a performance degradation of one order
 of magnitude versus an equivalent ASIC implementations, but low cost 
-(500 euros to 10K euros), fast time to market and flexibility of FPGAs make them an attractive 
+(500 euros to 10K euros), fast time-to-market and flexibility of FPGAs make them an attractive 
 choice for low-to-medium volume applications. 
 Since their introduction in the mid eighties, FPGAs evolved from a simple, 
@@ -61 +61 @@
 \parlf
 This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion
-of FPGA-based solutions is limited by the lack of design flow automation.
+of FPGA-based solutions is limited by the lack of design automation.
 Nowadays, there are neither commercial nor academic tools covering the whole design process
 from the system level specification to the bit stream generation.
-\\
 % IA to Alain: J'ai remis (et ameliore un peu) ca car sinon le Consequently 20 lignes
 %              au dessous n'a pas de sens.
 % Deplus dans les demandes ANR de la section, il est demande: analyse de la concurrence
-For instance, with SOPC Builder~\cite{spoc-builder} from \altera, designers can select and
+By using SOPC Builder~\cite{spoc-builder} from \altera, designers can select and
 parameterize components from an extensive drop-down list of IP cores (I/O core, DSP,
 processor,  bus core, ...) as well as incorporate their own IP.
@@ -79 +78 @@
 In addition, SOPC Builder is proprietary and only works together with \altera's Quartus compilation
 tool to implement designs on \altera devices (Stratix, Arria, Cyclone).
-\\
-For instance, PICO~\cite{pico} and CATAPULT-C~\cite{catapult-c} allow to synthesize
+PICO~\cite{pico} and CATAPULT-C~\cite{catapult-c} allow to synthesize
 coprocessors from a C++ description.
 Nevertheless, they can only deal with data dominated applications and they do not handle
 the platform level.
-\\
 Similarly, the System Generator for DSP~\cite{system-generateur-for-dsp} is a plug-in to
 Simulink that enables designers to develop high-performance DSP systems for \xilinx FPGAs.
@@ -95 +92 @@
 design environments:
 \begin{enumerate}
-  \item a virtual prototyping environment such as SoCLib for system level exploration,
+  \item a virtual prototyping environment for system level exploration,
   \item an architecture compiler (such as SOPC Builder from \altera, or System generator
   from \xilinx) to define the hardware architecture,
@@ -105 +102 @@
 the design process very complex and achievable only by designers skilled in many domains.
 \begin{center}\begin{minipage}{.8\linewidth}\textit{
-The aim of the COACH project is to integrate all these design steps into a single design framework.
+The aim of the COACH project is to integrate all these design steps into a single design framework
 and to allow \textbf{pure software} developpers to develop embedded systems.
 }\end{minipage}\end{center}
 \parlf
 We believe that the combination of a design environment dedicated to software developpers
-and the FPGA target,
-allows small and even very small companies to propose embedded system and accelerating solutions 
-for standard software applications with acceptable prices.
+and FPGA targets,
+will allow small and even very small companies to propose embedded system and accelerating solutions 
+for standard software applications with attractive and competitive prices.
 This new market may explode in the same way as the micro-computer market in the eighties,
 whose success was due to the low cost of the first micro-processors (compared to main frames)