Changeset 177 for anr

Timestamp:

Feb 15, 2010, 3:08:04 PM (15 years ago)

Author:

coach

Message:

UBS

File:

• anr/section-2.2.tex (modified) (4 diffs)

anr/section-2.2.tex

@@ -2 +2 @@
 % Relevance of the proposal 
 
-\mustbecompleted {FIXME == AJOUTER LES POINTS QUI SUIVENT sur les 3 axes ???}
-
---------------------------------------------------------------------------
-The COACH project answers to several of the challenges found in different axis of the call for proposals. Keywords of the call are indicated below in italic writing.
-
-Axis 1 "Architectures des syst\`{e}mes embarqu\'{e}s" :
-
-COACH will address new embedded systems architectures by allowing the design of  Multi-Core Systems-on-Chip (possibly heterogeneous) on FPGA according to the design constraints and objectives (real-time, low-power). It will permit to design  complex SoC  based on IP cores ((memory, peripherals, network controllers, communication processors), running Embedded Software, as well as an Operating System with associated middleware and API and using hardware accelerator automatically generated. It will also permit to use efficiently different dynamic system management techniques and re-configuration mechanisms. 
-
-Axis 2 "Infrastructures pour l'Internet, le calcul intensif ou les services" :
-
-COACH will address High-Performance Computing (HPC) by helping designer to accelerate an application running on a PC by migrating critical parts into a SoC implemented on an FPGA plugged to the PC bus (through a communication link like PCI/X). COACH will reduce the designer effort through the development of tools that translate high level language programs to FPGA configurations. Moreover, Dynamic Partial Reconfiguration will be used for improving HPC performance as well as reducing the required area.
-
-Axis 3 "Robotique et controle/commande" :
---------------------------------------------------------------------------
 
 
@@ -32 +17 @@
 environment, including communication middleware and tools to support
 developers in the production of embedded software, through all phases of the software lifecycle,
-from requirements analysis until deployment and maintenance.
+from requirements analysis downto deployment and maintenance.
 More specifically, COACH focuses on:
 \begin{itemize}
@@ -53 +38 @@
 %%%
 \parlf
-The COACH project will benefit from a number of previous projects:
+The COACH project will benefit from a number of previous recent projects:
 \begin{description}
   \item[SOCLIB]
     The SoCLib ANR platform (2007-2009) is an open infrastructure developped by 10 academic laboratories 
-    and 6 industrial companies. 
+    (TIMA, LIP6, Lab-STICC, IRISA, ENST, Gipsa-Lab, CEA-LIST, CEA-LETI, CITI, INRIA-Futurs, LIS) and 6 
+        industrial companies (Thales Communications, Thomson R\&D, STMicroelectronics, Silicomp, MDS, TurboConcept). 
     It supports system level virtual prototyping of shared memory, multi-processors
     architectures, and provides tools to map multi-tasks software application on these
@@ -125 +111 @@
 \end{itemize}
 %%%
+
+
+The COACH project answers to several of the challenges found in different axis of the 
+call for proposals. Keywords of the call are indicated below in italic writing.
+
+Axis 1 "Architectures des syst\`{e}mes embarqu\'{e}s" :
+
+COACH will address new embedded systems architectures by allowing the design of 
+Multi-Core Systems-on-Chip (possibly heterogeneous) on FPGA according to the design 
+constraints and objectives (real-time, low-power). It will permit to design  complex SoC 
+based on IP cores (memory, peripherals, network controllers, communication processors), 
+running Embedded Software, as well as an Operating System with associated middleware and 
+API and using hardware accelerator automatically generated. It will also permit to use 
+efficiently different dynamic system management techniques and re-configuration mechanisms. 
+
+Axis 2 "Infrastructures pour l'Internet, le calcul intensif ou les services" :
+
+COACH will address High-Performance Computing (HPC) by helping designer to accelerate an 
+application running on a PC by migrating critical parts into a SoC implemented on an FPGA 
+plugged to the PC bus (through a communication link like PCI/X). COACH will reduce the designer 
+effort through the development of tools that translate high level language programs to FPGA 
+configurations. Moreover, Dynamic Partial Reconfiguration will be used for improving HPC performance 
+as well as reducing the required area.
+
+Axis 3 "Robotique et controle/commande" :
+
+COACH will permit to design complex digital systems based on high-performance multi-core systems.
+Like in the consumer electronics domain (telecommunication, multimedia), future control applications 
+will employ more and more SoC not just for typical consumer functionality, but also for safety and 
+security applications (by performing complex analyses on data gathered with intelligent sensors, 
+by initiating appropriate responses to dangerous phenomena...). Application domains for such systems 
+are for example the automotive domain, as well as the aerospace and avionics domains (i.e. sophisticated on-board 
+radar systems, collision-detection, intelligent navigation...). 
+Manufacturing technology will also increasingly need high-end vision analysis and high-speed 
+robot control. In all cases, high performance and real time requirements are combined with 
+requirements to low power, low temperature, high dependability, and low cost.
+
+Axis 5 "S\'{e}curit\'{e} et suret\'{e}" :
+
+The results of the COACH project will help users to build cryptographic secure systems implemented in
+hardware or both in software/ hardware in an effective way, substantially enhancing the
+process productivity of the cryptographic algorithms hardware synthesis, improving the
+quality and reducing the design time and the cost of synthesised cryptographic devices.
+
+COACH technologies can be used in both large and small business, as they will permit users to design
+embedded systems which meet a wide range of requirements: from low cost and low power consuming
+devices to very high speed devices, based on parallel computing. For enterprises that will use embedded
+systems designed via the approaches and tools targeted by COACH, there is the potential for greater
+efficiency, improved business processes and models. The net results: lower costs, faster response times,
+better service, and higher revenue.
+
+
 \parlf
-Finally, it is worth to note that this project cover priorities defined by the commission 
+Finally, it is worth to note that this project covers priorities defined by the commission 
 experts in the field of Information Technolgies Society (IST) for Embedded
 Systems: $<<$Concepts, methods and tools for designing systems dealing with systems complexity