Changeset 182 for anr

Timestamp:

Feb 15, 2010, 4:03:09 PM (15 years ago)

Author:

coach

Message:

UBS

File:

• anr/section-3.2.tex (modified) (4 diffs)

anr/section-3.2.tex

@@ -6 +6 @@
 \begin{figure}[hbtp]\leavevmode\center
   \includegraphics[width=.8\linewidth]{flow}
-  \caption{\label{coach-flow} COACH flow}
+  \caption{\label{coach-flow} COACH design flow}
 \end{figure}
 \begin{description}
 \item[HPC setup:] During this step, the user splits the application into 2 parts: the host application
 which remains on a PC and the SoC application which is mapped on the FPGA. 
-The COACH framework provides a SystemC simulation model of the whole system (PC+communication+FPGA-SoC) which allows a performance evaluation of the partitioning.
+The COACH framework will provide a SystemC simulation model of the whole system (PC+communication+FPGA-SoC) which will allow performance evaluation of the partitioning.
 \item[SoC design:] In this phase, 
-the user can obtain simulators for the SoC at different abstraction levels by giving to the COACH framework a SoC description.  
-This description consists of a process network corresponding to the SoC application, 
+the user will be able to obtain simulators for the SoC at different abstraction levels by giving to the COACH framework a SoC description.  
+This description will consist of a process network corresponding to the SoC application, 
 an OS, an instance of a generic hardware platform
 and a mapping of processes on the platform components. The supported mapping are 
@@ -20 +20 @@
 ASIP (the process runs on a SoC processor enhanced with dedicated instructions),
 and hardware (the process runs into a coprocessor that is generated by HLS and plugged on the SoC bus).
-\item[Application compilation:] Once the SoC description is validated, COACH generates automatically
+\item[Application compilation:] Once the SoC description is validated, COACH will generate automatically
 an FPGA bitstream containing the hardware platform with the SoC application software and 
-an executable containing the host application. The user can launch the application by
+an executable containing the host application. The user will be able to launch the application by
 loading the bitstream on an FPGA and running the executable on PC.
 \end{description}
@@ -29 +29 @@
 % ambitieux du projet. 
 %FIXME == {NON ceci n'est pas une contribution scientifique. A re-ecrire}
-The main scientific contribution of the project is to unify various synthesis techniques
-(same input and output formats) allowing the user to swap without engineering effort
-from one to another and even to chain them. For instance, it will be possible to run loop transformations before synthesis.
-Another advantage of this framework is to provide different abstraction levels from
-a single description.
-Finally, this description is device family independent and its hardware implementation
-is automatically generated.
+
+%The main scientific contribution of the project is to unify various synthesis techniques
+%(same input and output formats) allowing the user to swap without engineering effort
+%from one to another and even to chain them. For instance, it will be possible to run loop transformations before synthesis.
+%Another advantage of this framework is to provide different abstraction levels from
+%a single description.
+%Finally, this description is device family independent and its hardware implementation
+%is automatically generated.
 
 % Detailler les verrous scientifiques et techniques a lever par la realisation du projet.
-System design is a very complicated task and in this project we try to simplify it
+System design is a very complicated task and in this project we will try to simplify it
 as much as possible. For this purpose we have to deal with the following scientific
 and technological barriers.
@@ -44 +45 @@
 \item HLS tools are sensitive to the style in which the algorithm is written.
 In addition, they are are not integrated into an architecture and system 
-exploration tool.
-Consequently, engineering work is required to swap from a tool to another,
+exploration tool. Consequently, engineering work is required to swap from a tool to another,
 to integrate the resulting simulation model to an architectural exploration tool 
 and to synthesize the generated RTL description.