Changeset 183 for anr


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Timestamp:
Feb 15, 2010, 4:11:16 PM (15 years ago)
Author:
coach
Message:

UBS

File:
1 edited

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  • anr/section-4.1.tex

    r134 r183  
    3030controls the HAS tools described below.
    3131From these inputs \verb!CSG! can generate the entire system (both software \&
    32 hardware) either as a SystemC simulator to prototype and explore quickly the
     32hardware) either as a SystemC simulator (cycla accurate and/or TLM) to prototype and explore quickly the
    3333design space or as a bitstream\footnote{COACH generates synthesizable VHDL, and
    3434launch the \xilinx or \altera RTL synthesis tools.} directly downloadable on the
     
    4040directly on the C++ task description but on an internal format called
    4141\xcoach generated by a plugin into the GNU C compiler (GCC).
    42 This allows on the one hand to insure that all the tools will
     42This will allow on the one hand to insure that all the tools will
    4343accept the same C++ description and on the other hand make possible
    4444their chaining. The front-end tools read a \xcoach description and generate
     
    6969    the internal formats (e.g. \xcoach), the architectural templates and
    7070    the design flow.
    71 \item[task-3: \textit{System generation}] This task addresses the prototyping and
    72     the generation of digital system. Apart from HAS that belong to task 3
     71\item[Task-3: \textit{System generation}] This task addresses the prototyping and
     72    the generation of digital system. Apart from HAS that belongs to task 3
    7373    and 4, its components are those presented figure~\ref{archi-csg}
    7474    (e.g.  \verb!CSG!, operating systems).
     
    8484\item[Task-6: \textit{PC/FPGA communication middleware}]
    8585    This task pools the features dedicated to HPC. These are mainly the
    86     partitioning validation (see figure~\ref{archi-hpc}), the sytem drivers for
     86    validation of the partitioning (see figure~\ref{archi-hpc}), the sytem drivers for
    8787    both PC and FPGA-SoC sides, the hardware communication components and
    88         support for dynamic partial reconfiguration.
     88        the support for dynamic partial reconfiguration.
    8989\item[Task-7: \textit{Industrial demonstrators}]
    9090    This task groups the demonstrators of the COACH project.
     
    9393    Others consist in integrating the COACH framework as a driver of
    9494    industrial proprietary design tools.
    95 \item{Task 8: \textit{Dissemination}}
     95\item[Task 8: \textit{Dissemination}]
    9696    This task concerns the diffusion of the project results.
    9797    It mainly consists of the production of 4 COACH releases (\verb!T0+12!, \verb!T0+18!,
    98     \verb!T0+24! and \verb!T0+36!)
    99     and the publication of a tutorial on a WEB site.
     98    \verb!T0+24! and \verb!T0+36!), the publication of a tutorial and user manuals on a WEB site, the publication
     99        of research papers in international journals and conferences and the organization of workshops and tutorials in
     100        international conferences.
    100101\end{description}
    101102%
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