Changeset 195 for anr


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Timestamp:
Feb 16, 2010, 8:04:07 AM (15 years ago)
Author:
coach
Message:

UBS

File:
1 edited

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  • anr/section-4.4.tex

    r179 r195  
    3636    written in the COACH input format. This COACH release allows to prototype and to generate the FPGA-SoC.
    3737    The main restrictions are:
    38     1) only the neutral architectural template is supported,
     38    1) Only the neutral architectural template is supported,
    3939    2) HAS is not available (but prototyping with virtual coprocessors is available),
    4040    3) Enhanced communication schemes are not available.
     
    4949    The main restriction are:
    5050    1) The backend HAS tools have not been yet enhanced,
    51     2) dynamic partial reconfiguration is not supported,
     51    2) Dynamic partial reconfiguration is not supported,
    5252    3) NIOS processor instruction set extension is supported, but only for user specified patterns.
    5353        4)\mustbecompleted{FIXME:ALL .....}
     
    5555       
    5656\end{description}
    57 This organisation allows to advance globally the project step by step mixing development
     57This organisation allows the project to globally progress step by step mixing development
    5858and demonstrator deliverables.
    5959Hence, demonstrator feed-back will arrive early and so the risk to point out incompatibility
     
    7777\item[Virtual prototyping of \altera \& \xilinx architectural templates ({\csgAlteraSystemC},
    7878     {\csgXilinxSystemC})]
    79      The SocLib component library contains several SystemC models used for the virtual
     79     The SoCLib component library contains several SystemC models used for the virtual
    8080     prototyping of the \altera and \xilinx architectural templates (NIOS and Microblaze processor cores).
    8181     Nevertheless, at this time we do not know how many IP cores SystemC simulation models have to be developped.
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