Changeset 21 for anr/task-1.tex


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Timestamp:
Dec 31, 2009, 8:27:21 AM (15 years ago)
Author:
coach
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1 edited

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  • anr/task-1.tex

    r12 r21  
     1%\def\TBresp{\coussy}
     2%\def\TBresplab{\labsticc}
     3%\def\TBpartner{\alllabs,\allcompagnies}
     4
     5\begin{taskinfo}
     6\let\UPMC\leader
     7\let\ALL\enable
     8\end{taskinfo}
     9%
     10\begin{objectif}
     11This task relies to the main features for embedded system.
     12Its objective consists of the specification of designer input, of the
     13definition of the hardware architectural templates and of all the features
     14that the HAS tools share.
     15\end{objectif}
     16%
     17\begin{workpackage}{T1}
     18\item This \ST specifies COACH for the system designer. At this
     19    level COACH is a black box. The deliverable is a document allowing the system
     20    designers to use COACH: feeding it (inputs), how to use it (design flow),
     21    what COACH can generate (definition of the generic architecture of the
     22    MPSoC and its 3 targets hardware mapping).
     23    \begin{livrable}
     24    \item{-1-V1}{0}{6}{d}{LIP6}{user manual}
     25        The first milestone of the document for allowing demonstration
     26        \ST to start.
     27    \item{-1-V1}{6}{18}{d}{LIP6}{user manual}
     28        The second milestone takes into account the missing features
     29        the demonstrators rise.
     30    \item{-1-VF}{18}{30}{d}{LIP6}{user manual}
     31        Final release.
     32    \end{livrable}
     33\item This \ST specifies the software COACH structure. The deliverable is a
     34    document listing all the COACH software components and how they cooperate.
     35    \begin{livrable}
     36    \item{}{0}{6}{d}{LIP6}{decription of software architecture}
     37        It contains the software list and the data flow among them.
     38    \end{livrable}
     39\item This \ST specifies the \xcoach format.
     40    \begin{livrable}
     41    \item{-1-V1}{0}{6}{d x}{LIP}{specification of \xcoach format}
     42        First release of the XML specification of the \xcoach format
     43        and its associated documentation allowing to start HLS tools development.
     44    \item{-1-V2}{6}{12}{d x}{LIP}{specification of \xcoach format}
     45        Second release of XML specification of the \xcoach format
     46        taking into account the corrections and modifications that the
     47        developers of HLS tools rise.
     48    \item{-1-VF}{12}{18}{d x}{LIP}{C++ to \xcoach format}
     49        Release of XML specification of the \xcoach format enhanced with
     50        the expression of loop potential.
     51    \item{-2-V1}{0}{12}{x x}{\ubs}{C++ to/from \xcoach format}
     52        The first executable generates a \xcoach description
     53        version \taskname-3-V1 from a C++ description of a task defined in \ST
     54        \taskname-1.
     55        The second program regenerates a C description from a \xcoach
     56        description.
     57    \item{-2-VF}{12}{18}{x x}{\ubs}{C++ to/from \xcoach format}
     58        The same programs as the former but for \xcoach format version \name-3-V2.
     59    \item{-3-V1}{0}{18}{x}{LIP6}{\xcoach format to SystemC}
     60        The first release of a program that translates \xcoach description to CABA
     61        and TLM-DT SystemC.
     62    \item{-3-VF}{18}{24}{x}{LIP6}{\xcoach format to SystemC}
     63        The \name-3-V1 deliverable without bugs reported by the demonstrators.
     64    \item{-4-V1}{0}{18}{x}{\ubs}{\xcoach format to VHDL}
     65        The first release of a program that translates \xcoach description to
     66        synthesizable VHDL description.
     67    \item{-4-VF}{18}{24}{x}{\ubs}{\xcoach format to VHDL}
     68        The \name-4-V1 deliverable without bugs reported by the demonstrators.
     69    \end{livrable}
     70\item Backend HLS tools use a characterized macro-cell library to build the
     71    micro-architecture of a coprocessor. The characterisation of a cell dépends
     72    on the target device. The role of this \ST is to define the macro-cells and
     73    to provite a tool that characterizes them automatically by synthesizing them
     74    and by extracting their delays. This is done by using RTL synthesis.
     75    \begin{livrable}
     76    \item{-1-VF}{0}{6}{d}{\ubs}{macro-cell definition}
     77        The document define the macro cell and the file format describing them.
     78    \item{-2-VF}{0}{12}{x}{\ubs}{macro-cell library generator}
     79        A progam that generates automatically the characterized macro-cell library
     80        for a FPGA device.
     81    \end{livrable}
     82\end{workpackage}
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