Changeset 216


Ignore:
Timestamp:
Feb 16, 2010, 10:57:58 AM (15 years ago)
Author:
coach
Message:

UBS

Location:
anr
Files:
2 edited

Legend:

Unmodified
Added
Removed
  • anr/task-1.tex

    r215 r216  
    105105        Final release of the former software (\specXcoachToVhdlI) and integration
    106106        of enhancements proposed in \novers{\specXilinxOptimization} deliverable.
    107     \itemL{18}{21}{d}{\Sxilinx}{\xilinx RTL optimisation (1)}{0:3:0}
     107    \itemL{18}{21}{d}{\Sxilinx}{\xilinx RTL optim. (1)}{0:3:0}
    108108        \setMacroInAuxFile{specXilinxOptimization}
    109109        This deliverable consists in optimizing the VHDL generated from \xcoachplus format
  • anr/task-2.tex

    r207 r216  
    3030\subtask This \ST corresponds to the COACH System Generator (CSG) software.
    3131    \begin{livrable}
    32     \itemV{0}{12}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgCoachArch}
     32    \itemV{0}{12}{x}{\Supmc}{CSG tool} \setMacroInAuxFile{csgCoachArch}
    3333        The first software release of the CSG tool that will allow demonstrators to start
    3434        working by using the neutral architectural template.
     
    4040        This milestone extends CSG (\csgPrototypingOnly) to
    4141        FPGA-SoC generation for the \xilinx and \altera architectural template.
    42     \itemL{24}{36}{x}{\Supmc}{CSG}{6:5.5:5.5}
     42    \itemL{24}{36}{x}{\Supmc}{CSG tool}{6:5.5:5.5}
    4343        Final release of CSG.
    4444    \end{livrable}
     
    5454    For the \xilinx and \altera architectural templates, we use the \xilinx and \altera IPs (NIOS, Microblaze, memories, busses...).
    5555    \begin{livrable}
    56     \itemL{0}{12}{h}{\Supmc}{neutral architecture}{1:0:0}
     56    \itemL{0}{12}{h}{\Supmc}{Neutral architecture}{1:0:0}
    5757        \setMacroInAuxFile{csgCoachArchTempl}
    5858        The VHDL synthesizable descriptions of the SocLib MWMR, TokenRing components.
    59     \itemL{12}{15}{d}{\Sxilinx}{\xilinx RTL optimisation (2)}{0:2:0}
     59    \itemL{12}{15}{d}{\Sxilinx}{\xilinx RTL optim. (2)}{0:2:0}
    6060       This deliverable consists in optimizing the VHDL descriptions of the components of
    6161       the neutral architectural template (deliverable \novers{\csgCoachArchTempl}) to the
     
    7171        The synthesizable VHDL description of the MWMR component corresponding to the
    7272        SystemC module of the former deliverable (\csgXilinxSystemC).
    73     \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (3)}{0:0:1.5}
     73    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optim. (3)}{0:0:1.5}
    7474       This deliverable consists in optimizing the MWMR VHDL description (deliverable
    7575       \novers{\csgXilinxSystemC}) of the \xilinx architectural template.
     
    9494       Final release of the tool that generates the VHDL description of the optimized
    9595       communication adapter and its corresponding SystemC module (\gautCOMMoptimization).
    96     \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (4)}{0:0:1.5}
     96    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optim. (4)}{0:0:1.5}
    9797       This deliverable consists in optimizing the communication adapter VHDL description (deliverable
    9898       \novers{\gautCOMMoptimization}).
     
    108108    \itemV{6}{8}{x}{\Supmc}{MUTEKH OS}
    109109        The drivers required for the first CSG milestone (deliverable \csgCoachArch).
    110     \itemV{8}{18}{x}{\Supmc}{MUTEKH 0S}
     110    \itemV{8}{18}{x}{\Supmc}{MUTEKH 0S drivers}
    111111        The drivers required for the second CSG milestone ({\csgPrototypingOnly}).
    112     \itemL{18}{33}{x}{\Supmc}{MUTEKH OS}{1:1:2}
     112    \itemL{18}{33}{x}{\Supmc}{MUTEKH OS drivers}{1:1:2}
    113113        Final release of the MUTEKH OS drivers.
    114     \itemL{6}{18}{x}{\Supmc}{Port of MUTEKH OS}{1.0:1:0}
     114    \itemL{6}{18}{x}{\Supmc}{Porting of MUTEKH OS}{1.0:1:0}
    115115        Porting of MUTEKH OS on the NIOS2 and MICROBLAZE processors.
    116116    \itemV{6}{8}{x}{\Stima}{DNA OS}
     
    118118    \itemV{8}{18}{x}{\Stima}{DNA 0S}
    119119        The drivers required for the second CSG milestone ({\csgPrototypingOnly}).
    120     \itemL{18}{33}{x}{\Stima}{DNA OS}{6:3:2}
     120    \itemL{18}{33}{x}{\Stima}{DNA OS drivers}{6:3:2}
    121121        Final release of the DNA OS drivers.
    122     \itemL{6}{18}{x}{\Stima}{Port of DNA OS}{3:1:0}
     122    \itemL{6}{18}{x}{\Stima}{Porting of DNA OS}{3:1:0}
    123123        Porting of DNA OS on the NIOS2 and MICROBLAZE processors.
    124124    \end{livrable}
Note: See TracChangeset for help on using the changeset viewer.