Changeset 216

Timestamp:

Feb 16, 2010, 10:57:58 AM (15 years ago)

Author:

coach

Message:

UBS

Location:

anr

Files:

• task-1.tex (modified) (1 diff)
• task-2.tex (modified) (7 diffs)

anr/task-1.tex

@@ -105 +105 @@
         Final release of the former software (\specXcoachToVhdlI) and integration
         of enhancements proposed in \novers{\specXilinxOptimization} deliverable.
-    \itemL{18}{21}{d}{\Sxilinx}{\xilinx RTL optimisation (1)}{0:3:0}
+    \itemL{18}{21}{d}{\Sxilinx}{\xilinx RTL optim. (1)}{0:3:0}
         \setMacroInAuxFile{specXilinxOptimization}
         This deliverable consists in optimizing the VHDL generated from \xcoachplus format

anr/task-2.tex

@@ -30 +30 @@
 \subtask This \ST corresponds to the COACH System Generator (CSG) software.
     \begin{livrable}
-    \itemV{0}{12}{x}{\Supmc}{CSG} \setMacroInAuxFile{csgCoachArch}
+    \itemV{0}{12}{x}{\Supmc}{CSG tool} \setMacroInAuxFile{csgCoachArch}
         The first software release of the CSG tool that will allow demonstrators to start
         working by using the neutral architectural template.
@@ -40 +40 @@
         This milestone extends CSG (\csgPrototypingOnly) to
         FPGA-SoC generation for the \xilinx and \altera architectural template.
-    \itemL{24}{36}{x}{\Supmc}{CSG}{6:5.5:5.5}
+    \itemL{24}{36}{x}{\Supmc}{CSG tool}{6:5.5:5.5}
         Final release of CSG.
     \end{livrable}
@@ -54 +54 @@
     For the \xilinx and \altera architectural templates, we use the \xilinx and \altera IPs (NIOS, Microblaze, memories, busses...).
     \begin{livrable}
-    \itemL{0}{12}{h}{\Supmc}{neutral architecture}{1:0:0}
+    \itemL{0}{12}{h}{\Supmc}{Neutral architecture}{1:0:0}
         \setMacroInAuxFile{csgCoachArchTempl}
         The VHDL synthesizable descriptions of the SocLib MWMR, TokenRing components.
-    \itemL{12}{15}{d}{\Sxilinx}{\xilinx RTL optimisation (2)}{0:2:0}
+    \itemL{12}{15}{d}{\Sxilinx}{\xilinx RTL optim. (2)}{0:2:0}
        This deliverable consists in optimizing the VHDL descriptions of the components of
        the neutral architectural template (deliverable \novers{\csgCoachArchTempl}) to the
@@ -71 +71 @@
         The synthesizable VHDL description of the MWMR component corresponding to the
         SystemC module of the former deliverable (\csgXilinxSystemC).
-    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (3)}{0:0:1.5}
+    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optim. (3)}{0:0:1.5}
        This deliverable consists in optimizing the MWMR VHDL description (deliverable
        \novers{\csgXilinxSystemC}) of the \xilinx architectural template.
@@ -94 +94 @@
        Final release of the tool that generates the VHDL description of the optimized
        communication adapter and its corresponding SystemC module (\gautCOMMoptimization).
-    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (4)}{0:0:1.5}
+    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optim. (4)}{0:0:1.5}
        This deliverable consists in optimizing the communication adapter VHDL description (deliverable
        \novers{\gautCOMMoptimization}).
@@ -108 +108 @@
     \itemV{6}{8}{x}{\Supmc}{MUTEKH OS}
         The drivers required for the first CSG milestone (deliverable \csgCoachArch).
-    \itemV{8}{18}{x}{\Supmc}{MUTEKH 0S}
+    \itemV{8}{18}{x}{\Supmc}{MUTEKH 0S drivers}
         The drivers required for the second CSG milestone ({\csgPrototypingOnly}).
-    \itemL{18}{33}{x}{\Supmc}{MUTEKH OS}{1:1:2}
+    \itemL{18}{33}{x}{\Supmc}{MUTEKH OS drivers}{1:1:2}
         Final release of the MUTEKH OS drivers.
-    \itemL{6}{18}{x}{\Supmc}{Port of MUTEKH OS}{1.0:1:0}
+    \itemL{6}{18}{x}{\Supmc}{Porting of MUTEKH OS}{1.0:1:0}
         Porting of MUTEKH OS on the NIOS2 and MICROBLAZE processors.
     \itemV{6}{8}{x}{\Stima}{DNA OS}
@@ -118 +118 @@
     \itemV{8}{18}{x}{\Stima}{DNA 0S}
         The drivers required for the second CSG milestone ({\csgPrototypingOnly}).
-    \itemL{18}{33}{x}{\Stima}{DNA OS}{6:3:2}
+    \itemL{18}{33}{x}{\Stima}{DNA OS drivers}{6:3:2}
         Final release of the DNA OS drivers.
-    \itemL{6}{18}{x}{\Stima}{Port of DNA OS}{3:1:0}
+    \itemL{6}{18}{x}{\Stima}{Porting of DNA OS}{3:1:0}
         Porting of DNA OS on the NIOS2 and MICROBLAZE processors.
     \end{livrable}