Changeset 217

Timestamp:

Feb 16, 2010, 11:01:26 AM (14 years ago)

Author:

coach

Message:

UBS

Location:

anr

Files:

• task-2.tex (modified) (1 diff)
• task-3.tex (modified) (2 diffs)

anr/task-2.tex

@@ -84 +84 @@
         The synthesizable VHDL description of the MWMR component corresponding to the
         SystemC module of the former deliverable (\csgAlteraSystemC);
-    \itemL{6}{12}{d}{\Subs}{UBS communication adapter}{1:0:0}
+    \itemL{6}{12}{d}{\Subs}{Communication adapter spec.}{1:0:0}
        \setMacroInAuxFile{gautCOMMoptimization}
        Specification of an optimized communication adapter (space and time) component to handle data interleaving.
        This evolution aims to solve out of order communication weakness of the classical MWMR. 
-    \itemV{12}{24}{x}{\Subs}{UBS communication adapter}{0:6:0}
+    \itemV{12}{24}{x}{\Subs}{Communication adapter}{0:6:0}
        First release of the tool that generates the VHDL description of the optimized communication adapter
        and its corresponding SystemC module. 
-    \itemL{24}{30}{x}{\Subs}{UBS communication adapter}{0:6:2}
+    \itemL{24}{30}{x}{\Subs}{Comm. adapter generator}{0:6:2}
        Final release of the tool that generates the VHDL description of the optimized
        communication adapter and its corresponding SystemC module (\gautCOMMoptimization).

anr/task-3.tex

@@ -51 +51 @@
       \itemV{12}{18}{h}{\Sirisa}{VHDL for an extensible MIPS}
       {A synthesizable VHDL model for a simple extensible MIPS architectural template}
-      \itemL{18}{24}{h}{\Sirisa}{VHDL for an extensible MIPS}{9:12:0}
+      \itemL{18}{24}{h}{\Sirisa}{VHDL for extensible MIPS}{9:12:0}
       {A synthesizable VHDL model for an extensible MIPS with a tight architectural integration of
       its instruction set extensions}
@@ -76 +76 @@
       Extension of automatic parallelization and array contraction
       to non-polyhedral loops. Implementation in the Bee framework.
-    \itemL{30}{36}{x}{\Slip} {Process and FIFO construction}{20:20:20}
+    \itemL{30}{36}{x}{\Slip} {Process/FIFO construction}{20:20:20}
       Final release taking into account the feedbacks from the 
       demonstrator \STs.