Changeset 23


Ignore:
Timestamp:
Jan 7, 2010, 12:24:14 PM (15 years ago)
Author:
coach
Message:
 
Location:
anr
Files:
3 added
2 edited

Legend:

Unmodified
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  • anr/anr.tex

    r21 r23  
    3838\def\ubs{UBS\xspace}    % LAB-STICC
    3939\def\upmc{LIP6\xspace}
     40\def\altera{ALTERA\xspace}
     41\def\xilinx{XILINX\xspace}
    4042\def\bull{BULL\xspace}
    4143\def\thales{THALES\xspace}
     
    203205\subsubsection{Task 1: \textit{\backbone}}
    204206\input{task-1}
     207
     208\subsubsection{Task 2: \textit{system generation}}
     209\input{task-2}
     210
     211\subsubsection{Task 3: \textit{HAS front-end}}
     212%\input{task-3}
     213
     214\subsubsection{Task 4: \textit{HAS back-end}}
     215%\input{task-4}
     216
     217\subsubsection{Task 5: \textit{Communication between PC \& FPGA-SoC}}
     218\input{task-5}
     219
     220\subsubsection{Task 6: \textit{Demonstrators}}
     221\input{task-6}
    205222
    206223\subsection{Tasks schedule, deliverables and milestones}
  • anr/section-4.1.tex

    r21 r23  
    9494    partitioning validation (see figure~\ref{archi-hpc}, the sytem drivers for
    9595    both PC and FPGA-SoC sides, the hardware communication components.
    96 \item\textbf{Demonstrator:}
     96\item\textbf{Demonstrators:}
    9797    This task groups the demostrators of the COACH project.
    9898    \mustbecompleted{FIXME}
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