Changeset 236


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Timestamp:
Feb 16, 2010, 5:06:32 PM (15 years ago)
Author:
coach
Message:

UBS

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1 edited

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  • anr/section-2.2.tex

    r233 r236  
    3939  \item[SOCLIB]
    4040    The SoCLib ANR platform (2007-2009) is an open infrastructure developped by
    41     10 academic laboratories and and 6 industrial companies. It supports
    42     system level virtual prototyping of shared memory, multi-processors
    43     architectures. It provides tools to map multi-tasks software application on these
    44     (TIMA, LIP6, Lab-STICC, IRISA, ENST, CEA-LIST, CEA-LETI, CITI, INRIA-Futurs, LIS) and 6
     41    10 academic laboratories (TIMA, LIP6, Lab-STICC, IRISA, ENST, CEA-LIST, CEA-LETI, CITI, INRIA-Futurs, LIS) and 6
    4542    industrial companies (Thales Communications, Thomson R\&D, STMicroelectronics, Silicomp, MDS, TurboConcept).
    4643    It supports system level virtual prototyping of shared memory, multi-processors
     
    5249    communication middleware.
    5350    The synthesisable VHDL models of IPs are not part of the SoCLib platform, and
    54     this project enhances SoCLib by providing the synthesisable VHDL models required
     51    COACH will enhance SoCLib by providing the synthesisable VHDL models required
    5552    for FPGA synthesis.
    56     The synthesisable VHDL models of IPs are not part of the SoCLib platform, and
    57     this project enhances SoCLib by providing them.
    5853  \item[ROMA] The ROMA ANR project \cite{roma}
    5954    involving IRISA (CAIRN team), LIRMM, CEA List THOMSON France R\&D,
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