Changeset 237


Ignore:
Timestamp:
Feb 16, 2010, 5:24:12 PM (15 years ago)
Author:
coach
Message:

Paul coquilles

Location:
anr
Files:
13 edited

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  • anr/section-2.1.tex

    r173 r237  
    4242on chip A/D conversion, and gate counts by millions. This high logic capacity allows to implement
    4343complex systems like multi-processors platform with application dedicated coprocessors.
    44 Table~\ref{fpga_market} shows the estimation of FPGA worldwide market in the next years in
     44Table~\ref{fpga_market} shows the estimation of the FPGA worldwide market in the next years in
    4545various application domains. The ``high end'' lines concern only FPGA with high logic
    4646capacity for complex system implementations.

  • anr/section-2.2.tex

    r236 r237  
    5252    for FPGA synthesis.
    5353  \item[ROMA] The ROMA ANR project \cite{roma}
    54     involving IRISA (CAIRN team), LIRMM, CEA List THOMSON France R\&D,
     54    involving IRISA (CAIRN team), LIRMM, CEA List, THOMSON France R\&D,
    5555    proposes to develop a reconfigurable processor, exhibiting high
    5656    silicon density and power efficiency, able to adapt its computing
    5757    structure to computation patterns that can be speed-up and/or
    58     power efficient.  The ROMA project study a pipeline-based of
     58    power efficient.  The ROMA project study a pipeline of
    5959    evolved low-power coarse grain reconfigurable operators to avoid
    6060    traditional overhead, in reconfigurable devices, related to the
    … …  
    6666%    ASIP processors.
    6767  \item[TSAR]
    68      The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and the \upmc targets the design of a
     68     The TSAR MEDEA+ project (2008-2010) involving BULL, THALES and \upmc targets the design of a
    6969%    The TSAR MEDEA+ project (2008-2010) targets the design of a
    7070    scalable, coherent shared memory, multi-cores processor architecture, and uses the SoCLib
    … …  
    118118COACH will address new embedded systems architectures by allowing the design of
    119119Multi-Core Systems-on-Chip (possibly heterogeneous) on FPGA according to the design
    120 constraints and objectives (real-time, low-power). It will permit to design  complex SoC
     120constraints and objectives (real-time, low-power). It will permit designing  complex SoC
    121121based on IP cores (memory, peripherals, network controllers, communication processors),
    122122running Embedded Software, as well as an Operating System with associated middleware and
    … …  
    126126%
    127127\item[Axis 2] \textit{Infrastructures pour l'Internet, le calcul intensif ou les services} \\
    128 COACH will address High-Performance Computing (HPC) by helping designer to accelerate an
     128COACH will address High-Performance Computing (HPC) by helping designers to accelerate an
    129129application running on a PC by migrating critical parts into a SoC implemented on an FPGA
    130130plugged to the PC bus (through a communication link like PCI/X). COACH will reduce the designer

  • anr/section-2.tex

    r172 r237  
    1 Embedded systems (SoC and MPSoC) became an inevitable evolution in microelectronic industry.
     1Embedded systems (SoC and MPSoC) became an inevitable evolution in the microelectronic industry.
    22Due to the exploding fabrication costs, the ASIC technology (Application Specific Integrated Circuit)
    33is not an option for SMEs (Small and Medium Enterprises).
    … …  
    2121The COACH project will leverage on the expertise gained in the field of virtual prototyping
    2222with the SoCLib platform, to propose a new design flow based on a small number of architectural templates.
    23 An architectural template is a generic, parametrized architecture, relying on a predefined library
     23An architectural template is a generic, parameterized architecture, relying on a predefined library
    2424of IP cores.
    2525Besides using a specific collection of general purpose IP cores (such as processors cores,

  • anr/section-3.1.tex

    r235 r237  
    88\subsubsection{High Performance Computing}
    99% Un marché bouffé par les archi GPGPU tel que le FERMI de NvidiaCUDA programming language
    10 High-Performance Computing (HPC) world is composed of three main families of architectures:
     10The High-Performance Computing (HPC) world is composed of three main families of architectures:
    1111many-core, GPGPU (General Purpose computation on Graphics Unit Processing) and FPGA.
    12 The two first families are dominating the market by taking benefit
     12The first  two families are dominating the market by taking benefit
    1313of the strength and influence of mass-market leaders (Intel, Nvidia).
    1414%such as Intel for many-core CPU and Nvidia for GPGPU.
    … …  
    5151\subsubsection{System Synthesis}
    5252Today, several solutions for system design are proposed and commercialized.
    53 The existing commercial or free tools does not
     53The existing commercial or free tools do not
    5454cover the whole system synthesis process in a full automatic way. Moreover,
    5555they are bound to a particular device family and to IPs library.
    … …  
    8484set of constraints (area, power, frequency, ...) to a micro-architecture at
    8585Register Transfer Level (RTL).
    86 Several academic and commercial tools are today available. Most common
     86Several academic and commercial tools are today available. The most common
    8787tools are SPARK~\cite{spark04}, GAUT~\cite{gaut08}, UGH~\cite{ugh08} in the
    8888academic world and CATAPULTC~\cite{catapult-c}, PICO~\cite{pico} and
    89 CYNTHETIZER~\cite{cynthetizer} in commercial world.  Despite their
     89CYNTHETIZER~\cite{cynthetizer} in the commercial world.  Despite their
    9090maturity, their usage is restrained by \cite{IEEEDT} \cite{CATRENE} \cite{HLSBOOK}:
    9191\begin{itemize}
    … …  
    9898designs are multi-constrained,
    9999Moreover, low power consumption constraint is mandatory for embedded systems.
    100 However, it is not yet well handled or not handle at all by the synthesis tools already available,
     100However, it is not yet well handled or not handled at all by the synthesis tools already available,
    101101\item The parallelism is extracted from initial algorithmic specification.
    102102To get more parallelism or to reduce the amount of required memory in the SoC, the user
    … …  
    106106pipelining, current HLS tools do not provide support for design space exploration neither
    107107through automatic loop transformations nor through memory mapping,
    108 \item Despite they have the same input language (C/C++), they are sensitive to the style in
    109 which the algorithm is written. Consequently, engineering work is required to swap from
     108\item Despite having the same input language (C/C++), they are sensitive to the style in
     109which the algorithm dis written. Consequently, engineering work is required to swap from
    110110a tool to another,
    111111\item They do not respect accurately the frequency constraint when they target an FPGA device.
    112112Their error is about 10 percent. This is annoying when the generated component is integrated
    113 in a SoC since it will slow down the hole system.
     113in a SoC since it will slow down the whole system.
    114114\end{itemize}
    115115Regarding these limitations, it is necessary to create a new tool generation reducing the gap

  • anr/section-3.2.tex

    r235 r237  
    113113the required performance of a coprocessor (clock frequency, maximum cycles for
    114114a given computation, power consumption, etc) are imposed by the other system
    115 components. The challenge is to allow user to control accurately the synthesis
     115components. The challenge is to allow the user to control accurately the synthesis
    116116process. For instance, the clock frequency must not be a result of the RTL synthesis
    117117but a strict synthesis constraint.

  • anr/section-4.1.tex

    r183 r237  
    6060is done through \verb!CSG! (figure~\ref{archi-csg}).
    6161\parlf
    62 The project is split into 8 tasks numbered from 1 to 8. There are described
    63 below and detailled in section \ref{task-description}.
     62The project is split into 8 tasks numbered from 1 to 8. They are described
     63in short below and in detail in section \ref{task-description}.
    6464\begin{description}
    6565\item[Task-1: \textit{Project management}]

  • anr/section-5.tex

    r196 r237  
    22
    33The COACH project will bring new scientific results in various fields, such as high level synthesis,
    4 hardware/software codesign, virtual prototyping, harware oriented compilation techniques,
     4hardware/software codesign, virtual prototyping, hardware oriented compilation techniques,
    55automatic parallelisation, etc. These results will be published in relevant International
    66Conferences, namely DATE, DAC, or ICCAD.
    … …  
    1515
    1616Following the general policy of the SoCLib platform, the COACH project will be an
    17 open infrastructure, and the COACH tools and libraries will available in the framework
     17open infrastructure, and the COACH tools and libraries will be available in the framework
    1818of the SoCLib WEB server. This server will be maintened by the UPMC/LIP6 laboratory.
    1919

  • anr/task-0.tex

    r231 r237  
    3232        Global management of the project at all the
    3333        levels: progress monitoring, record keeping, meeting organization, review
    34         organization, the writting of the review reports.
     34        organization, the writing of the review reports.
    3535    \end{livrable}
    36   \subtask This \ST consists managing the project at the partner level.
     36  \subtask This \ST consists in managing the project at the partner level.
    3737    It includes mainly the progress monitoring, the record keeping the participation to the
    3838    project meetings and the communication with the project leader and the other partners.

  • anr/task-1.tex

    r231 r237  
    109109        \setMacroInAuxFile{specXilinxOptimization}
    110110        This deliverable consists in optimizing the VHDL generated from \xcoachplus format
    111         (deliverable \novers{\specXcoachToVhdl}) to the \xilinx RTL synthesis tools.
     111        (deliverable \novers{\specXcoachToVhdl}) for the \xilinx RTL synthesis tools.
    112112        \ubs will provide several examples of VHDL source files generated from \xcoachplus,
    113113        with explanations about generation process of main data structures used in VHDL sources,

  • anr/task-2.tex

    r217 r237  
    1111Its is described on figure~\ref{archi-csg}.
    1212Its objective is to allow the system designer to explore the design space by
    13 quickly prototyping and then to automatically generate the FPGA-SoC system.
     13quickly prototyping and then to automatically generate the FPGA-SoC systems.
    1414This task consists of
    1515\begin{itemize}
    … …  
    2323This task being based on the SoCLib platform, a first release will be delivered at $T0+12$
    2424to allow the demonstrators to start working.
    25 This release will include the standard communication schemes (base on SoCLib MWMR component)
     25This release will include the standard communication schemes (based on SoCLib MWMR component)
    2626and support the neutral architectural template for prototyping and hardware generation.
    2727\end{objectif}

  • anr/task-3.tex

    r224 r237  
    6363   \begin{livrable}
    6464    \itemV{0}{6}{d}{\Slip}{Method, Preliminary Definition}
    65       Description and specification work construction method for programs with
     65      Description and specification of a process construction method for programs with
    6666      polyhedral loops.
    6767    \itemL{30}{36}{d}{\Slip}{Process generation method}{10:0:9}

  • anr/task-5.tex

    r231 r237  
    2525
    2626The low level hardware transmission support will be the PCI/X bus which allows high bit-rate
    27 transfers. The reasons of this choices are that both \altera and \xilinx provide PCI/X IP for
     27transfers. The reasons of this choice are that both \altera and \xilinx provide PCI/X IP for
    2828their FPGA and that GPU HPC softwares use also it.
    2929%This will allow us at least to be inspired by GPU communication schemes and may be to reuse
    … …  
    9090    \begin{livrable}
    9191    \itemL{24}{36}{x}{\Supmc}{CSG support for \ganttlf reconfiguration}{0:0:2}
    92         Modification of CSG software to support statically reconfigurable task.
     92        Modification of the CSG software to support statically reconfigurable tasks.
    9393    \itemL{18}{36}{x}{\Stima}{CSG module for \ganttlf dynamic reconfiguration}{0:4:12}
    94                 This livrable is a CSG module allowing to partition the task graph on
     94                This livrable is a CSG module allowing to partition the task graph along
    9595                the dynamic partial reconfiguration regions. The resulting task-region assignement
    9696                is directly used for generation of bitstreams. The module also produces reconfiguration

  • anr/task-7.tex

    r231 r237  
    55%
    66\begin{objectif}
    7 This task relies to the diffusion of the project results.
     7This task relates to the diffusion of the project results.
    88The objective is to ensure the COACH dissemination by publishing on a public WEB site all
    99the information that a COACH user requires.
    … …  
    2020%
    2121\begin{workpackage}
    22   \subtask This \ST relies to the management of the WEB site and to the distribution of
     22  \subtask This \ST relates to the management of the WEB site and to the distribution of
    2323    the COACH releases.
    2424    \begin{livrable}
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