Changeset 243


Ignore:
Timestamp:
Feb 16, 2010, 10:02:02 PM (15 years ago)
Author:
coach
Message:

IA

Location:
anr
Files:
5 edited

Legend:

Unmodified
Added
Removed
  • anr/section-4.4.tex

    r195 r243  
    1515
    1616\begin{figure}\leavevmode\center
    17 \hspace*{-.6cm}\vspace{-1.5cm}
     17\hspace*{-.4cm}%\vspace{-1.5cm}
    1818\input{gantt1.tex}
    19 \caption{\label{gantt1}Gantt diagram of deliverables (task-1 to task-4)}
     19\caption{\label{gantt1}Gantt diagram of deliverables (task-1 to task-4 and task-8)}
    2020\end{figure}
    2121
    2222\begin{figure}\leavevmode\center
    23 \hspace*{-.6cm}\vspace{-1.5cm}
     23\hspace*{-.4cm}%\vspace{-1.5cm}
    2424\input{gantt2.tex}
    25 \caption{\label{gantt2}Gantt diagram of deliverables (task-5 to task-8)}
     25\caption{\label{gantt2}Gantt diagram of deliverables (task-5, task-6 and task-7)}
    2626\end{figure}
    2727
  • anr/task-1.tex

    r237 r243  
    106106        Final release of the former software (\specXcoachToVhdlI) and integration
    107107        of enhancements proposed in \novers{\specXilinxOptimization} deliverable.
    108     \itemL{18}{21}{d}{\Sxilinx}{\xilinx RTL optim. (1)}{0:3:0}
     108    \itemL{18}{21}{d}{\Sxilinx}{\xilinx RTL optimization (1)}{0:3:0}
    109109        \setMacroInAuxFile{specXilinxOptimization}
    110110        This deliverable consists in optimizing the VHDL generated from \xcoachplus format
  • anr/task-2.tex

    r237 r243  
    5757        \setMacroInAuxFile{csgCoachArchTempl}
    5858        The VHDL synthesizable descriptions of the SocLib MWMR, TokenRing components.
    59     \itemL{12}{15}{d}{\Sxilinx}{\xilinx RTL optim. (2)}{0:2:0}
     59    \itemL{12}{15}{d}{\Sxilinx}{\xilinx RTL optimization (2)}{0:2:0}
    6060       This deliverable consists in optimizing the VHDL descriptions of the components of
    6161       the neutral architectural template (deliverable \novers{\csgCoachArchTempl}) to the
     
    7171        The synthesizable VHDL description of the MWMR component corresponding to the
    7272        SystemC module of the former deliverable (\csgXilinxSystemC).
    73     \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optim. (3)}{0:0:1.5}
     73    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimization (3)}{0:0:1.5}
    7474       This deliverable consists in optimizing the MWMR VHDL description (deliverable
    7575       \novers{\csgXilinxSystemC}) of the \xilinx architectural template.
     
    9494       Final release of the tool that generates the VHDL description of the optimized
    9595       communication adapter and its corresponding SystemC module (\gautCOMMoptimization).
    96     \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optim. (4)}{0:0:1.5}
     96    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimization (4)}{0:0:1.5}
    9797       This deliverable consists in optimizing the communication adapter VHDL description (deliverable
    9898       \novers{\gautCOMMoptimization}).
  • anr/task-4.tex

    r223 r243  
    9191        The frequency calibration software consists of a driver in the FPGA-SoC operating
    9292        system and of a control software.
    93     \itemL{24}{27}{d}{\Sxilinx}{Optimisation for \ganttlf \xilinx RTL tools (5)}{0:0:1.5}
     93    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimization (5)}{0:0:1.5}
    9494       This deliverable consists in optimizing the VHDL description provided in
    9595       \novers{\freqCalibrationVhdl}.
  • anr/task-7.tex

    r239 r243  
    5959    \itemL{30}{36}{d}{\Supmc}{Tutorial}{2:1:1}
    6060        The final release of the tutorial.
    61     \itemL{30}{33}{d}{\Sxilinx}{Feedback for \ganttlf \xilinx RTL tools}{0:0:0.5}
    62         \xilinx will check that developped tutorial works well with \xilinx tools,
     61    \itemL{30}{33}{d}{\Sxilinx}{\xilinx feedback}{0:0:0.5}
     62        \xilinx will check that the developped tutorial works well with \xilinx tools,
    6363        and will propose corrections or enhancements if needed into a document.
    6464    \end{livrable}
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