Changeset 244

Timestamp:

Feb 16, 2010, 10:08:08 PM (15 years ago)

Author:

coach

Message:

IA: typos

Location:

anr

Files:

• task-1.tex (modified) (1 diff)
• task-2.tex (modified) (3 diffs)
• task-4.tex (modified) (1 diff)

anr/task-1.tex

@@ -106 +106 @@
         Final release of the former software (\specXcoachToVhdlI) and integration
         of enhancements proposed in \novers{\specXilinxOptimization} deliverable.
-    \itemL{18}{21}{d}{\Sxilinx}{\xilinx RTL optimization (1)}{0:3:0}
+    \itemL{18}{21}{d}{\Sxilinx}{\xilinx RTL optimisation (1)}{0:3:0}
         \setMacroInAuxFile{specXilinxOptimization}
         This deliverable consists in optimizing the VHDL generated from \xcoachplus format

anr/task-2.tex

@@ -57 +57 @@
         \setMacroInAuxFile{csgCoachArchTempl}
         The VHDL synthesizable descriptions of the SocLib MWMR, TokenRing components.
-    \itemL{12}{15}{d}{\Sxilinx}{\xilinx RTL optimization (2)}{0:2:0}
+    \itemL{12}{15}{d}{\Sxilinx}{\xilinx RTL optimisation (2)}{0:2:0}
        This deliverable consists in optimizing the VHDL descriptions of the components of
        the neutral architectural template (deliverable \novers{\csgCoachArchTempl}) to the
@@ -71 +71 @@
         The synthesizable VHDL description of the MWMR component corresponding to the
         SystemC module of the former deliverable (\csgXilinxSystemC).
-    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimization (3)}{0:0:1.5}
+    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (3)}{0:0:1.5}
        This deliverable consists in optimizing the MWMR VHDL description (deliverable
        \novers{\csgXilinxSystemC}) of the \xilinx architectural template.
@@ -94 +94 @@
        Final release of the tool that generates the VHDL description of the optimized
        communication adapter and its corresponding SystemC module (\gautCOMMoptimization).
-    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimization (4)}{0:0:1.5}
+    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (4)}{0:0:1.5}
        This deliverable consists in optimizing the communication adapter VHDL description (deliverable
        \novers{\gautCOMMoptimization}).

anr/task-4.tex

@@ -91 +91 @@
         The frequency calibration software consists of a driver in the FPGA-SoC operating
         system and of a control software.
-    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimization (5)}{0:0:1.5}
+    \itemL{24}{27}{d}{\Sxilinx}{\xilinx RTL optimisation (5)}{0:0:1.5}
        This deliverable consists in optimizing the VHDL description provided in 
        \novers{\freqCalibrationVhdl}.