Changeset 249 for anr

Timestamp:

Feb 17, 2010, 3:15:29 PM (15 years ago)

Author:

coach

Message:

UBS

File:

• anr/section-3.2.tex (modified) (6 diffs)

anr/section-3.2.tex

@@ -44 +44 @@
 as much as possible. For this purpose the following scientific and technological barriers
 have to be addressed.
-
-\begin{description}
-\item[Design Space Exploration:]
+        \\
+        \\
+%\begin{description}
+%\item[]
+\textit{Design Space Exploration:}\\
     The COACH environment will allow to easily map an application described by using a process 
         network Model of Computation (MoC) on a shared-memory, MPSoC architecture. COACH will
@@ -52 +54 @@
         parameterize the target architecture, and to define the best hardware/software 
         partitioning of the application.
-
-\item[High-Level Synthesis:]
+        \\
+        \\
+%\item[High-Level Synthesis:]
+\textit{High-Level Synthesis:}\\
     COACH will allow the automatic generation of hardware accelerators when required
         by using High-Level Synthesis (HLS) tools.
@@ -62 +66 @@
     COACH will provide a tool which will automatically explore the micro-architectural 
         design space of coprocessor.
-
-\item[High-level code transformation:]
+\\
+        \\
+%\item[High-level code transformation:]
+\textit{High-level code transformation:}\\ 
     COACH will allow to optimize the memory usage, to enhance the parallelism through 
         loop transformations and parallelization. The challenge is to identify the coarse 
@@ -76 +82 @@
         Particularly, this includes parallelism exposure and efficient memory mapping.
         COACH will support code transformation by providing a source to source C2C tool.
-
-\item[Platform based design:] 
+\\
+        \\
+%\item[Platform based design:] 
+\textit{Platform based design: }\\
     COACH will define architectural templates that can be customized by adding
     dedicated coprocessors and ASIPs and by fixing template parameters such as
@@ -84 +92 @@
     However, the specification of the application will be independant of both the
     architectural template and the target FPGA device.
-
-\item[Hardware/Software communication middleware:]
+\\
+        \\
+%\item[Hardware/Software communication middleware:]
+\textit{Hardware/Software communication middleware: }\\
     COACH will implement an homogeneous HW/SW communication infrastructure and
     communication APIs (Application Programming Interface), that will be used for 
     communications between software tasks running on embedded processors and 
     dedicated hardware coprocessors. This will allow explore the design space by 
-        mapping the tasks of application (described as a process network) on a 
+        mapping the tasks of the application (described as a process network) on a 
         shared-memory, MPSoC architecture.
-
-\item[Processor customization:]
+\\
+        \\
+%\item[Processor customization:]
+\textit{Processor customization: }\\
 ASIP design will be addressed by the COACH project. COACH will allow system designers to explore 
 the various level of interactions between the original CPU micro-architecture and its
   extension. It will also allow to retarget the compiler instruction-selection pass. Finally,
  COACH will integrate ASIP design in a complete System-level design framework.
-
-\item [High-Performance Computing:] The main problem in HPC is the communication 
+\\
+        \\
+%\item [High-Performance Computing:] The main problem in HPC is the communication 
+\textit{High-Performance Computing: }\\
+The main problem in HPC is the communication 
 between the PC and the SoC. This problem has 2 aspects. The first one is the run-time 
 efficiency. The second is its engineering  cost, especially if one want to refine an 
 implementation at several abstract levels.
-COACH will 
-
+COACH will help designer to accelerate applications by migrating critical parts into a
+SoC embedded into an FPGA device plugged to the PC PCI/X bus.
+\\
 %\item The COACH design flow has a top-down approach. In such a case,
 %the required performance of a coprocessor (clock frequency, maximum cycles for
@@ -112 +128 @@
 %but a strict synthesis constraint.
 
-\end{description}
-
-
-
+%\end{description}
 
 %Presenter les resultats escomptes en proposant si possible des criteres de reussite