Changeset 260 for anr


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Timestamp:
Feb 18, 2010, 8:41:31 AM (15 years ago)
Author:
coach
Message:

UBS

File:
1 edited

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  • anr/task-6.tex

    r259 r260  
    139139  \subtask
    140140  The \navtel Embedded Supper Computing (ESC) project is based on simple hardware but tightly
    141   coupled module between ARM processor and FPGA.
    142   For the COACH project, \navtel will automatically synthetize two cores: one for software radio
     141  coupled module between %ARM
     142  a embedded processor and an FPGA both on a board.
     143  By using the COACH environment, \navtel will automatically synthetize two cores: one for software radio
    143144  through a polyphase resampler and one for an industrial control application through an embedded
    144145  PID controller.
    145   The objective is to sequence the cores in realtime in FPGA using partial configuration methods.
     146  The objective is to sequence the cores in realtime in FPGA using partial configuration methods
     147  proposed in the COACH project.
    146148  This will allow us to gain experience on automatic multi core sequencing at system level. The
    147149  specification for our first work package will concern this aspect.
     
    149151  The ESC can function on different topologies: Single, parallel or Grid computing modes for
    150152  industrial and scientific applications.
    151   The ARM and FPGA configuration also facilitate the co-simulation which allows to  gain
     153  %The ARM
     154  The processor and FPGA configuration also facilitate the co-simulation which allows to  gain
    152155  time on the development and integration phase.
    153156  The architecture consists of a wrapper that encapsules computing units depending on the
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