Changeset 269 for anr

Timestamp:

Feb 20, 2010, 12:29:50 PM (15 years ago)

Author:

coach

Message:

IA: finale

Location:

anr

Files:

• anr.tex (modified) (1 diff)
• coach.pdf (added)
• section-1.tex (modified) (1 diff)
• section-3.2.tex (modified) (5 diffs)

anr/anr.tex

@@ -134 +134 @@
     \vspace*{0.5ex}Total requested \\ funding
   \end{minipage}
-    & \makebox[3cm]{\mustbecompleted{XXXX} \euro}
+    & \makebox[3cm]{1195931 \euro}
       & \begin{minipage}{4.15cm}\center Project Duration \end{minipage}
         & \begin{minipage}{3cm}\center 36 months \end{minipage} \\\hline

anr/section-1.tex

@@ -158 +158 @@
 the technology providers are ready to propose commercial licenses, directly to the end user,
 or through a third party.
+\parlf
+Finally, the COACH project is already supported by a large number of PMEs, as demonstrated by the 
+"letters of interest" (see Annex B), that have collected during the preparation of the project :
+ADACSYS, MDS, INPIXAL, CAMKA System, ATEME, ALSIM, SILICOMP-AQL,
+ABOUND Logic, EADS-ASTRIUM.
 

anr/section-3.2.tex

@@ -1 +1 @@
 % les objectifs scientifiques/techniques du projet.
-The objectives of the COACH project are to develop a complete framework to HPC
-(accelerating solutions for existing software applications) and embedded
-applications (implementing an application on a low power standalone
-device).  The design steps are presented figure~\ref{coach-flow}.
+The design steps are presented figure~\ref{coach-flow}.
 \begin{figure}[hbtp]\leavevmode\center
   \includegraphics[width=.8\linewidth]{flow}
@@ -10 +7 @@
 \begin{description}
 \item[HPC setup:] During this step, the user splits the application into 2 parts: the host application
-which remains on a PC and the SoC application which is mapped on the FPGA. 
-COACH will allow to automatically translate high level language programs to FPGA configurations.
-In addition, it will provide a SystemC simulation model of the whole system (PC+communication+FPGA-SoC) 
-which will allow performance evaluation of the partitioning.
+which remains on the PC and the SoC application which is mapped on the FPGA. 
+COACH will provide a complete simulation model of the whole system (PC+communication+FPGA-SoC) 
+which will allow performance evaluation.
 \item[SoC design:] In this phase, 
-COACH will allow the user to obtain simulators for the SoC at different abstraction levels by giving to the COACH framework a SoC description.  
-This description will consist of a process network corresponding to the application, 
-an OS, an instance of a generic hardware platform
-and a mapping of processes on the platform components. COACH will offer different targets to map the processes:  
-software (the process runs on a SoC processor),
-ASIP (the process runs on a SoC processor enhanced with dedicated instructions),
-and hardware (the process runs into a coprocessor that is generated by HLS and plugged on the SoC bus).
-\item[Application compilation:] Once the SoC description is validated through performances analysis, COACH will generate automatically
-an FPGA bitstream containing the hardware platform with the SoC application software and 
-an executable containing the host application. The user will be able to launch the application by
+COACH will allow the user to obtain virtual prototypes for the SoC at different abstraction levels.
+The user input will consist of a process network describing the coarse grain parallelism
+of the application, an instance of a generic hardware platform
+and a mapping of processes on the platform components. 
+COACH will offer different targets to map the processes:  
+software (the process runs as a software task on a SoC processor),
+ASIP (the process runs as a software task on a SoC processor enhanced with dedicated instructions),
+and hardware (the process is implemented as a synthesized hardware coprocessor).
+\item[Application compilation:] Once the SoC architecture is validated through performances 
+analysis, COACH will generate automatically an executable containing the host application and
+the FPGA bitstream. This bitstream contains 
+both the hardware architecture and the SoC application software.
+The user will be able to launch the application by
 loading the bitstream on an FPGA and running the executable on PC.
 \end{description}
@@ -41 +40 @@
 
 % Detailler les verrous scientifiques et techniques a lever par la realisation du projet.
-System design is a very complex task and in this project we will try to simplify it
-as much as possible. For this purpose the following scientific and technological barriers
-have to be addressed.
-        \\
-        \\
-%\begin{description}
-%\item[]
-\textit{Design Space Exploration:}\\
-    The COACH environment will allow to easily map an application described by using a process 
+Hardware/Software co-design is a very complex task. To simplify it, COACH will address the
+following scientific and technological barriers:
+\begin{description}
+\item[\textit{Design Space Exploration by Virtual Prototyping}]:
+    The COACH environment will allow to easily map a parallel application described as a process 
         network Model of Computation (MoC) on a shared-memory, MPSoC architecture. COACH will
         permit to explore the design space by allowing system designer to select and 
         parameterize the target architecture, and to define the best hardware/software 
         partitioning of the application.
-        \\
-        \\
-%\item[High-Level Synthesis:]
-\textit{High-Level Synthesis:}\\
+\item[\textit{High-Level Synthesis}]:
     COACH will allow the automatic generation of hardware accelerators when required
-        by using High-Level Synthesis (HLS) tools.
-        HLS will thus be fully integrated into a complete system-level design environment.
-        Moreover, COACH will support both data and control dominated applications. 
-    Indeed, the HLS tools of COACH will support a common language and coding style 
+        by using High-Level Synthesis (HLS) tools. These HLS tools will be
+        fully integrated into a complete system-level design environment.
+        Moreover, COACH will support both data and control dominated applications,
+    and the HLS tools of COACH will support a common language and coding style 
         to avoid re-engineering by the designer.
     COACH will provide a tool which will automatically explore the micro-architectural 
         design space of coprocessor.
-\\
-        \\
-%\item[High-level code transformation:]
-\textit{High-level code transformation:}\\ 
+\item[\textit{High-level code transformation}]:
     COACH will allow to optimize the memory usage, to enhance the parallelism through 
         loop transformations and parallelization. The challenge is to identify the coarse 
@@ -82 +71 @@
         Particularly, this includes parallelism exposure and efficient memory mapping.
         COACH will support code transformation by providing a source to source C2C tool.
-\\
-        \\
-%\item[Platform based design:] 
-\textit{Platform based design: }\\
-    COACH will define architectural templates that can be customized by adding
-    dedicated coprocessors and ASIPs and by fixing template parameters such as
-    the number of embedded processors, the number of sizes of embedded memory banks
-    or the embedded the operating system.
-    However, the specification of the application will be independant of both the
-    architectural template and the target FPGA device.
-\\
-        \\
-%\item[Hardware/Software communication middleware:]
-\textit{Hardware/Software communication middleware: }\\
+\item[\textit{Hardware/Software communication middleware}]:
     COACH will implement an homogeneous HW/SW communication infrastructure and
     communication APIs (Application Programming Interface), that will be used for 
@@ -102 +78 @@
         mapping the tasks of the application (described as a process network) on a 
         shared-memory, MPSoC architecture.
-\\
-        \\
-%\item[Processor customization:]
-\textit{Processor customization: }\\
+\item[\textit{Processor customization}]:
 ASIP design will be addressed by the COACH project. COACH will allow system designers to explore 
 the various level of interactions between the original CPU micro-architecture and its
   extension. It will also allow to retarget the compiler instruction-selection pass. Finally,
  COACH will integrate ASIP design in a complete System-level design framework.
-\\
-        \\
-%\item [High-Performance Computing:] The main problem in HPC is the communication 
-\textit{High-Performance Computing: }\\
-The main problem in HPC is the communication 
-between the PC and the SoC. This problem has 2 aspects. The first one is the run-time 
-efficiency. The second is its engineering  cost, especially if one want to refine an 
-implementation at several abstract levels.
-COACH will help designer to accelerate applications by migrating critical parts into a
-SoC embedded into an FPGA device plugged to the PC PCI/X bus.
-\\
-%\item The COACH design flow has a top-down approach. In such a case,
-%the required performance of a coprocessor (clock frequency, maximum cycles for
-%a given computation, power consumption, etc) are imposed by the other system
-%components. The challenge is to allow the user to control accurately the synthesis
-%process. For instance, the clock frequency must not be a result of the RTL synthesis
-%but a strict synthesis constraint.
-
-%\end{description}
+\end{description}
 
 %Presenter les resultats escomptes en proposant si possible des criteres de reussite