Changeset 269 for anr/section-3.2.tex


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Feb 20, 2010, 12:29:50 PM (15 years ago)
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coach
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IA: finale

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  • anr/section-3.2.tex

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    11% les objectifs scientifiques/techniques du projet.
    2 The objectives of the COACH project are to develop a complete framework to HPC
    3 (accelerating solutions for existing software applications) and embedded
    4 applications (implementing an application on a low power standalone
    5 device).  The design steps are presented figure~\ref{coach-flow}.
     2The design steps are presented figure~\ref{coach-flow}.
    63\begin{figure}[hbtp]\leavevmode\center
    74  \includegraphics[width=.8\linewidth]{flow}
    … …  
    107\begin{description}
    118\item[HPC setup:] During this step, the user splits the application into 2 parts: the host application
    12 which remains on a PC and the SoC application which is mapped on the FPGA.
    13 COACH will allow to automatically translate high level language programs to FPGA configurations.
    14 In addition, it will provide a SystemC simulation model of the whole system (PC+communication+FPGA-SoC)
    15 which will allow performance evaluation of the partitioning.
     9which remains on the PC and the SoC application which is mapped on the FPGA.
     10COACH will provide a complete simulation model of the whole system (PC+communication+FPGA-SoC)
     11which will allow performance evaluation.
    1612\item[SoC design:] In this phase,
    17 COACH will allow the user to obtain simulators for the SoC at different abstraction levels by giving to the COACH framework a SoC description. 
    18 This description will consist of a process network corresponding to the application,
    19 an OS, an instance of a generic hardware platform
    20 and a mapping of processes on the platform components. COACH will offer different targets to map the processes: 
    21 software (the process runs on a SoC processor),
    22 ASIP (the process runs on a SoC processor enhanced with dedicated instructions),
    23 and hardware (the process runs into a coprocessor that is generated by HLS and plugged on the SoC bus).
    24 \item[Application compilation:] Once the SoC description is validated through performances analysis, COACH will generate automatically
    25 an FPGA bitstream containing the hardware platform with the SoC application software and
    26 an executable containing the host application. The user will be able to launch the application by
     13COACH will allow the user to obtain virtual prototypes for the SoC at different abstraction levels.
     14The user input will consist of a process network describing the coarse grain parallelism
     15of the application, an instance of a generic hardware platform
     16and a mapping of processes on the platform components.
     17COACH will offer different targets to map the processes: 
     18software (the process runs as a software task on a SoC processor),
     19ASIP (the process runs as a software task on a SoC processor enhanced with dedicated instructions),
     20and hardware (the process is implemented as a synthesized hardware coprocessor).
     21\item[Application compilation:] Once the SoC architecture is validated through performances
     22analysis, COACH will generate automatically an executable containing the host application and
     23the FPGA bitstream. This bitstream contains
     24both the hardware architecture and the SoC application software.
     25The user will be able to launch the application by
    2726loading the bitstream on an FPGA and running the executable on PC.
    2827\end{description}
    … …  
    4140
    4241% Detailler les verrous scientifiques et techniques a lever par la realisation du projet.
    43 System design is a very complex task and in this project we will try to simplify it
    44 as much as possible. For this purpose the following scientific and technological barriers
    45 have to be addressed.
    46         \\
    47         \\
    48 %\begin{description}
    49 %\item[]
    50 \textit{Design Space Exploration:}\\
    51     The COACH environment will allow to easily map an application described by using a process
     42Hardware/Software co-design is a very complex task. To simplify it, COACH will address the
     43following scientific and technological barriers:
     44\begin{description}
     45\item[\textit{Design Space Exploration by Virtual Prototyping}]:
     46    The COACH environment will allow to easily map a parallel application described as a process
    5247        network Model of Computation (MoC) on a shared-memory, MPSoC architecture. COACH will
    5348        permit to explore the design space by allowing system designer to select and
    5449        parameterize the target architecture, and to define the best hardware/software
    5550        partitioning of the application.
    56         \\
    57         \\
    58 %\item[High-Level Synthesis:]
    59 \textit{High-Level Synthesis:}\\
     51\item[\textit{High-Level Synthesis}]:
    6052    COACH will allow the automatic generation of hardware accelerators when required
    61         by using High-Level Synthesis (HLS) tools.
    62         HLS will thus be fully integrated into a complete system-level design environment.
    63         Moreover, COACH will support both data and control dominated applications.
    64     Indeed, the HLS tools of COACH will support a common language and coding style
     53        by using High-Level Synthesis (HLS) tools. These HLS tools will be
     54        fully integrated into a complete system-level design environment.
     55        Moreover, COACH will support both data and control dominated applications,
     56    and the HLS tools of COACH will support a common language and coding style
    6557        to avoid re-engineering by the designer.
    6658    COACH will provide a tool which will automatically explore the micro-architectural
    6759        design space of coprocessor.
    68 \\
    69         \\
    70 %\item[High-level code transformation:]
    71 \textit{High-level code transformation:}\\
     60\item[\textit{High-level code transformation}]:
    7261    COACH will allow to optimize the memory usage, to enhance the parallelism through
    7362        loop transformations and parallelization. The challenge is to identify the coarse
    … …  
    8271        Particularly, this includes parallelism exposure and efficient memory mapping.
    8372        COACH will support code transformation by providing a source to source C2C tool.
    84 \\
    85         \\
    86 %\item[Platform based design:]
    87 \textit{Platform based design: }\\
    88     COACH will define architectural templates that can be customized by adding
    89     dedicated coprocessors and ASIPs and by fixing template parameters such as
    90     the number of embedded processors, the number of sizes of embedded memory banks
    91     or the embedded the operating system.
    92     However, the specification of the application will be independant of both the
    93     architectural template and the target FPGA device.
    94 \\
    95         \\
    96 %\item[Hardware/Software communication middleware:]
    97 \textit{Hardware/Software communication middleware: }\\
     73\item[\textit{Hardware/Software communication middleware}]:
    9874    COACH will implement an homogeneous HW/SW communication infrastructure and
    9975    communication APIs (Application Programming Interface), that will be used for
    … …  
    10278        mapping the tasks of the application (described as a process network) on a
    10379        shared-memory, MPSoC architecture.
    104 \\
    105         \\
    106 %\item[Processor customization:]
    107 \textit{Processor customization: }\\
     80\item[\textit{Processor customization}]:
    10881ASIP design will be addressed by the COACH project. COACH will allow system designers to explore
    10982the various level of interactions between the original CPU micro-architecture and its
    11083  extension. It will also allow to retarget the compiler instruction-selection pass. Finally,
    11184 COACH will integrate ASIP design in a complete System-level design framework.
    112 \\
    113         \\
    114 %\item [High-Performance Computing:] The main problem in HPC is the communication
    115 \textit{High-Performance Computing: }\\
    116 The main problem in HPC is the communication
    117 between the PC and the SoC. This problem has 2 aspects. The first one is the run-time
    118 efficiency. The second is its engineering  cost, especially if one want to refine an
    119 implementation at several abstract levels.
    120 COACH will help designer to accelerate applications by migrating critical parts into a
    121 SoC embedded into an FPGA device plugged to the PC PCI/X bus.
    122 \\
    123 %\item The COACH design flow has a top-down approach. In such a case,
    124 %the required performance of a coprocessor (clock frequency, maximum cycles for
    125 %a given computation, power consumption, etc) are imposed by the other system
    126 %components. The challenge is to allow the user to control accurately the synthesis
    127 %process. For instance, the clock frequency must not be a result of the RTL synthesis
    128 %but a strict synthesis constraint.
    129 
    130 %\end{description}
     85\end{description}
    13186
    13287%Presenter les resultats escomptes en proposant si possible des criteres de reussite
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