Changeset 272 for anr/coach_summary.txt


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Feb 20, 2010, 5:00:49 PM (15 years ago)
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alain
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  • anr/coach_summary.txt

    r270 r272  
    1 The objective of COACH is to provide an integrated design flow, based on the
    2 SoCLib virtual prototyping infrastructure, and optimized for the design of
    3 multi-processors digital systems targeting FPGA devices.
    4 Such digital systems are generally integrated
    5 into one or several chips, and there are two types of applications:
    6 They can be embedded (autonomous) applications
    7 such as personal digital assistants (PDA), ambiant computing components,
    8 or wireless sensor networks (WSN).
    9 They can also be extension boards connected to a PC to accelerate a specific computation,
    10 as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP).
     1The objective of COACH is to provide an integrated design flow, based on the SoCLib virtual prototyping infrastructure, and optimized for the design of multi-processors digital systems targeting FPGA devices.  Such digital systems are generally integrated into one or several chips, and there are two types of applications:
     2- They can be embedded (autonomous) applications such as personal digital assistants (PDA), ambiant computing components, or wireless sensor networks (WSN).
     3- They can also be extension boards connected to a PC to accelerate a specific computation, as in High-Performance Computing (HPC) or High-Speed Signal Processing (HSSP).
    114
    125The COACH project will provide three hardware architectural templates:
    136
    14     - A Neutral architectural template based on the SoCLib IP core library and the
    15       VCI/OCP communication infrastructure.
    16     - An Altera architectural template based on the Altera IP core library, the
    17       AVALON system bus and the NIOS processor.
    18     - A Xilinx architectural template based on the Xilinx IP core library, the PLB
    19       system bus and the Microblaze processor.
     7    - A Neutral architectural template based on the SoCLib IP core library and the VCI/OCP communication infrastructure.
     8    - An Altera architectural template based on the Altera IP core library, the AVALON system bus and the NIOS processor.
     9    - A Xilinx architectural template based on the Xilinx IP core library, the PLB system bus and the Microblaze processor.
    2010
    21 The COACH design flow will be dedicated to system designers, and will as
    22 much as possible hide the hardware characteristics to the end-user.
    23 The specification of the application will be independant from the
    24 architectural template and the target FPGA device.
     11The COACH design flow will be dedicated to system designers, and will as much as possible hide the hardware characteristics to the end-user.  The specification of the application will be independant from the architectural template and the target FPGA device.
    2512
    26 To reach this ambitious goal, the project will rely on the experience and the
    27 complementariness of partners in the following domains:
    28 - Operating system and communication middleware (Tima, Lip6),
    29 - MPSoC architectures (Tima, Lab-Sticc, Lip6),
    30 - ASIP architectures (Inria/Cairn),
    31 - High Level Synthesis (Tima, Lab-Sticc, Lip6), and compilation (Ens-Lyon/Lip).
     13To reach this ambitious goal, the project will rely on the experience and the complementariness of partners in the following domains:
     14- Operating system and communication middleware (Tima, Lip6)
     15- MPSoC architectures (Tima, Lab-Sticc, Lip6)
     16- ASIP architectures (Inria/Cairn)
     17- High Level Synthesis (Tima, Lab-Sticc, Lip6), and compilation (Ens-Lyon/Lip)
    3218
    33 The COACH project does not start from scratch.
    34 It stronly relies on the SoCLib virtual prototyping platform for prototyping,
    35 (DSX, component library), operating systems (MUTEKH, DNA/OS).
    36 It also leverages on  several existing technologies: the GAUT and UGH tools for HLS,
    37 the ROMA project for ASIP, the SYNTOL and BEE tools for source-level analysis and transformations
    38 and on the Xilinx and Altera IP core libraries.
    39 Finally it will use the Xilinx and Altera logic and physical synthesis
    40 tools to generate the FPGA configuration bitstreams.
     19The COACH project does not start from scratch.  It stronly relies on the SoCLib virtual prototyping platform for prototyping, (DSX, component library), operating systems (MUTEKH, DNA/OS).  It also leverages on  several existing technologies: the GAUT and UGH tools for HLS, the ROMA project for ASIP, the SYNTOL and BEE tools for source-level analysis and transformations, and the Xilinx and Altera IP core libraries.  Finally it will use the Xilinx and Altera logic and physical synthesis tools to generate the FPGA configuration bitstreams.
    4120
    42 Two major FPGA companies are involved in the project: Xilinx will contribute
    43 as a contractual partner providing documentation and manpower; Altera will contribute as
    44 a supporter, providing documentation and development boards. These two companies are strongly motivated
    45 to help the COACH project to generate efficient bitsreams for both FPGA families.
    46 The role of the industrial partners Bull, Thales, Navtel and Flexras is to provide
    47 real use cases to benchmark the COACH design environment and to analyze the designer productivity
    48 improvements.
     21Two major FPGA companies are involved in the project: Xilinx will contribute as a contractual partner providing documentation and manpower; Altera will contribute as a supporter, providing documentation and development boards. These two companies are strongly motivated to help the COACH project to generate efficient bitsreams for both FPGA families.
    4922
    50 Following the general policy of the SoCLib platform, the COACH project will be an open
    51 infrastructure, available in the framework of the SoCLib server.
    52 The architectural templates, and the COACH software tools will be distributed under the
    53 GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib
    54 IP core library) will be freely available for non commercial use. For industrial exploitation
    55 the technology providers are ready to propose commercial licenses, directly to the end user,
    56 or through a third party.
     23The role of the industrial partners Bull, Thales, Navtel and Flexras is to provide real use cases to benchmark the COACH design environment and to evaluate the designer productivity improvements.
    5724
    58 Finally, the COACH project is already supported by a large number of PMEs, as demonstrated by the
    59 "letters of interest", that have collected during the preparation of the project :
    60 - ADACSYS
    61 - MDS
    62 - INPIXAL
    63 - CAMKA System
    64 - ATEME
    65 - ALSIM
    66 - SILICOMP-AQL
    67 - ABOUND Logic
    68 - EADS-ASTRIUM
     25Following the general policy of the SoCLib platform, the COACH project will be an open infrastructure, available in the framework of the SoCLib server.  The architectural templates, and the COACH software tools will be distributed under the GPL license. The VHDL synthesizable models for the neutral architectural template (SoCLib IP core library) will be freely available for non commercial use. For industrial exploitation the technology providers are ready to propose commercial licenses, directly to the end user, or through a third party.
     26
     27Finally, the COACH project is already supported by a large number of PMEs, as demonstrated by the "letters of interest", that have collected during the preparation of the project :
     28    - ADACSYS
     29    - MDS
     30    - INPIXAL
     31    - CAMKA System
     32    - ATEME
     33    - ALSIM
     34    - SILICOMP-AQL
     35    - ABOUND Logic
     36    - EADS-ASTRIUM
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