Changeset 280

Timestamp:

Nov 30, 2010, 6:11:33 PM (14 years ago)

Author:

coach

Message:

Changed design flow figure and corresponding text.

Location:

anr

Files:

• Makefile (modified) (1 diff)
• flow2.fig (added)
• section-3.2.tex (modified) (5 diffs)

anr/Makefile

@@ -3 +3 @@
 SOURCES=        anr.tex anr.bib anr.sty section-1.tex \
                         section-2.tex section-2.1.tex section-2.2.tex \
-                        flow.pdf section-3.1.tex section-3.2.tex \
+                        flow2.pdf section-3.1.tex section-3.2.tex \
                         task-0.tex task-1.tex task-2.tex task-3.tex \
                         task-4.tex task-5.tex task-6.tex \

anr/section-3.2.tex

@@ -5 +5 @@
 either a HPC application (an application running on a PC that must be accelarate),
 or an embedded application (a standalone application),
-or a sub-system application of a larger design.}
+or a  sub-system application of a larger design.
+The figure shows that the design flow of embedded and sub-system applications does not differ
+except in the generation step and that the design flow of HPC application just adds a
+preliminary step.
+}
 \begin{figure}[hbtp]\leavevmode\center
-  \includegraphics[width=.8\linewidth]{flow}
+  \includegraphics[width=1.0\linewidth]{flow2}
   \caption{\label{coach-flow} COACH design flow}
 \end{figure}
@@ -24 +28 @@
 ASIP (the process runs as a software task on a SoC processor enhanced with dedicated instructions),
 and hardware (the process is implemented as a synthesized hardware coprocessor).
+\begin{SUPPRESSEDENV}
 \item[Application compilation:]
-\begin{SUPPRESSEDENV}
 Once the SoC architecture is validated through performances analysis,
 COACH will generate automatically an executable containing the host application and
@@ -33 +37 @@
 loading the bitstream on an FPGA and running the executable on PC.
 \end{SUPPRESSEDENV}\begin{ADDEDENV}
+\item[Generation:]
 Once the SoC architecture is validated through performances analysis,
 COACH generates its bitstream in the case of HPC or embedded application,
@@ -60 +65 @@
 \begin{description}
 \item[\textit{Design Space Exploration by Virtual Prototyping}]:
-        The COACH environment will allow to easily map a parallel application (formally described as
-        an abstract network of process and communication channels)  
-        COACH will permit the system designer to explore the design space, and to define the best 
-        hardware/software partitioning of the application.
+    The COACH environment will allow to easily map a parallel application (formally described as
+    an abstract network of process and communication channels)  
+    COACH will permit the system designer to explore the design space, and to define the best 
+    hardware/software partitioning of the application.
 \item[\textit{Integration of system level modeling and HLS tools}]:
-        COACH will support the automated generation of hardware accelerators when required
-        by using High-Level Synthesis (HLS) tools. These HLS tools will be
-        fully integrated into a complete system-level design environment.
-        Moreover, COACH will support both data and control dominated applications,
-        and the HLS tools of COACH will support a common language and coding style 
-        to avoid re-engineering by the designer.
-        COACH will provide a tool which will automatically explore the micro-architectural 
-        design space of coprocessor.
+    COACH will support the automated generation of hardware accelerators when required
+    by using High-Level Synthesis (HLS) tools. These HLS tools will be
+    fully integrated into a complete system-level design environment.
+    Moreover, COACH will support both data and control dominated applications,
+    and the HLS tools of COACH will support a common language and coding style 
+    to avoid re-engineering by the designer.
+    COACH will provide a tool which will automatically explore the micro-architectural 
+    design space of coprocessor.
 \item[\textit{High-level code transformation}]:
-        COACH will allow to optimize the memory usage, to enhance the parallelism through 
-        loop transformations and parallelization. The challenge is to identify the coarse 
-        grained parallelism and to generate,
-        from a sequential algorithm, application containing multiple communicating
-        tasks. COACH will adapt techniques which were developed in the 1990 for 
-        the construction of distributed programs. However, in the context of HLS, there are 
-        several original problems to be solved, related to the  FIFO communication channels and with 
-        memory optimization. 
-        COACH will support code transformation by providing a source to source C2C tool.
+    COACH will allow to optimize the memory usage, to enhance the parallelism through 
+    loop transformations and parallelization. The challenge is to identify the coarse 
+    grained parallelism and to generate,
+    from a sequential algorithm, application containing multiple communicating
+    tasks. COACH will adapt techniques which were developed in the 1990 for 
+    the construction of distributed programs. However, in the context of HLS, there are 
+    several original problems to be solved, related to the  FIFO communication channels and with 
+    memory optimization. 
+    COACH will support code transformation by providing a source to source C2C tool.
 \item[\textit{Unified Hardware/Software communication middleware}]:
-        COACH will rely on he SoCLib experience to implement an unified hardware/software communication 
-        infrastructure and communication APIs (Application Programming Interface), to support  
-        communications between software tasks running on embedded processors and dedicated 
-        hardware coprocessors. The main issue here is to support easy migration 
-        from a software implementation to an hardware implementation.
+    COACH will rely on he SoCLib experience to implement an unified hardware/software communication 
+    infrastructure and communication APIs (Application Programming Interface), to support  
+    communications between software tasks running on embedded processors and dedicated 
+    hardware coprocessors. The main issue here is to support easy migration 
+    from a software implementation to an hardware implementation.
 \item[\textit{Processor customization}]:
-        ASIP (Application Specific Instruction Processor) design will be addressed by the COACH project. 
-        COACH will allow system designers to explore the various level of interactions between 
-        the original CPU micro-architecture and its extension. It will also allow to retarget 
-        the compiler instruction-selection pass. Finally, COACH will integrate ASIP synthesis
-        in a complete System-level design framework.
+    ASIP (Application Specific Instruction Processor) design will be addressed by the COACH project. 
+    COACH will allow system designers to explore the various level of interactions between 
+    the original CPU micro-architecture and its extension. It will also allow to retarget 
+    the compiler instruction-selection pass. Finally, COACH will integrate ASIP synthesis
+    in a complete System-level design framework.
 \end{description}
 
@@ -103 +108 @@
 a communication middleware for HPC, 
 5 HAS tools (control dominated HLS, data dominated HLS, Coarse grained HLS, 
-Memory optimisation HLS and ASIP),
+Memory optimization HLS and ASIP),
 3 architectural templates that are synthesizable and that can be prototyped,
 one design space exploration tool,
-2 operating systems (DNA/OS and MUTEKH).
+1 operating systems (DNA/OS).
 \\
-The framework fonctionality will be demonstrated with the demonstrators
+The framework functionalities will be demonstrated with the demonstrators
 (see task-7 page~\pageref{task-7}) and the tutorial example (see task-8
 page~\ref{subtask-tutorial}).