Changeset 283 for anr/section-6.1.tex

Timestamp:

Nov 30, 2010, 6:14:47 PM (14 years ago)

Author:

coach

Message:

Suppressed reference to Flexras and Navtel.

File:

• anr/section-6.1.tex (modified) (3 diffs)

anr/section-6.1.tex

@@ -152 +152 @@
 \parlf
 Even if the preferred dissemination policy for the COACH design flow will be the free
-software policy, (following the SoCLib model), the SoC department is ready to support
-start-ups : Six startup companies (including \zied) have been created by former
+software policy, the SoC department is ready to support start-ups :
+Six startup companies have been created by former
 researchers from  the SoC department of LIP6 between 1997 and 2002.
 
@@ -189 +189 @@
 the fact of the increase of the architecture complexity and due to the use of FPGA
 component for low power applications.
+
+%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
+\subsubsection{\mds}
+
+\mustbecompleted{Emanuel ....}
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
@@ -247 +252 @@
 computing embedded systems.
 
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsubsection{\zied}
-
-\zied is an innovative start-up specialized in the conception of configurable circuits
-and the development of CAD tools. \zied provides a complete front-to-back-end generator
-of "hardware" reprogrammable IP cores that can be embedded in ASIC and ASSP SoC designs.
-\zied solution is based on a patented FPGA architecture delivering an unprecedented
-level of logic density. This high capacity is accessible using a traditional RTL flow from
-Verilog/VHDL synthesis all the way to bitstream generation.
-\parlf
-\zied is a spin-off from LIP6 (Laboratoire Informatique Paris 6) and was awarded at the
-French National Competition for Business Startup and Innovative Technology in 2007 and
-2009 in "emergence" and "creation" categories respectively.
-
-%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\subsubsection{\navtel}
-
-\navtel was created in 1994 to develop flexible systems based on FPGAs and currently
-focuses on intelligent signal mining for knowlege based signal processing systems. 
-The company main activity covers the following domains: satellite communication,
-aeronautics, imaging and security.
-\navtel dedicates about 70\% of its activity to client projects in satellite, aeronautical
-and imaging systems and 30\% to its own research programmes in collaboration with French
-and international partners.
-\parlf
-The multi disciplinary technical team comprises 6 engineers for signal processing and
-hardware development and one technician.
-\parlf
-\navtel has its own Ph.D program which includes in the past (classification technology
-and MIMO for FPGA implementation) and currently the preparation of a project for remote
-sensing with signal intelligence for satellite application. The company participates in
-national and European level projects contributing to a strategic alliance between academic
-and  industrial partners.\\
-The current research covers particle filter applications for communication and RADAR,
-Cognitive Radio, Satellite communication, embedded super computing and focuses on low
-power algorithms for implementation in FPGA and  soft computing.
-\parlf
-For manufacturing and industrialization, \navtel works with ISO certified partners.
-The company clients include the CNES, Thal\`{e}s Alenia Space, Thal\`{e}s Communication, EADS,
-Eutelsat, AIRBUS, Schlumberger. \navtel participates from the R\&D phase up to the
-system delivery.
-\begin{description}
-\item[Recognitions:]\mbox{}
-\begin{itemize}
-  \item HEC Challenge+  program for innovative projects (promotion 9)
-  \item Innovation and technology development \og Troph\'{e}es R\'{e}gion Centre \fg
-  \item Recognition by the French Senate for company creation  during the
-        \og Semaine de l'entrepreneur \fg 2005.
-\end{itemize}
-\end{description}