- Timestamp:
- Dec 6, 2010, 5:26:44 PM (14 years ago)
- Location:
- anr
- Files:
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- 5 edited
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anr/section-4.1.tex
r277 r287 9 9 \mbox{}\vspace*{1ex}\\ 10 10 \includegraphics[width=.8\linewidth]{architecture-hpc} 11 \caption{\label{archi-hpc} Software architecture of HPC}11 \caption{\label{archi-hpc} Performance analysis of a HPC partitionning} 12 12 \end{figure} 13 13 % -
anr/task-1.tex
r279 r287 5 5 % 6 6 \begin{objectif} 7 This task deals with the main features of digital systems. 8 Its objectives are the specification of the designer input, the 7 The objectives of this task are the specification of the designer input, the 9 8 definition of the hardware architectural templates and of all the features 10 9 that the HAS tools will share. 10 An other objective is the specification of the framework used to facilitate the 11 exploitation and the integration of the core engine into an industrial flow. 11 12 \end{objectif} 12 13 % 13 14 \begin{workpackage} 14 15 \subtask{Specification of the COACH environment} 15 This \ST specifies the COACH environment for the system designer. In this 16 \ST the COACH framework is a black box. The deliverables are documents 17 specifying: how to feed COACH (the inputs), how to use COACH (use model), 18 what is generated (the outputs). 16 This \ST specifies the global COACH environment for the system designer: 17 the core engine which is seen as a black box associated 18 with a configuration framework based on Eclipse. 19 This framework will be integated into Magillem tool suite. 20 The deliverables specify 21 how to feed COACH (the inputs), 22 how to use COACH (use model), 23 what is generated (the outputs) 24 and how the Magillem framework iteracts with the core engine. 19 25 \begin{livrable} 20 26 \itemV{0}{6}{d}{\Supmc}{Use model specification} 21 This document describes the use mod leof COACH. It will be a cooperative work.27 This document describes the use model of COACH. It will be a cooperative work. 22 28 Its main parts are: 23 29 \begin{description} 24 30 \item[General overview] (\Supmc) 25 \item[CSG specification] (\Stima) 26 Here the COACH System Generator Generator is specified:31 \item[CSG specification] (\Stima): 32 here the COACH System Generator Generator is specified: 27 33 how the task graph is described, the communication schemes and 28 34 its associated API (Application Programming Interface). … … 31 37 Nevertheless, these basic schemes will be enhanced to allow more efficient 32 38 synthesis. 33 \item[HAS specification] (\Subs) 34 This part focuses to the Hardware Accelerator Synthesis.39 \item[HAS specification] (\Subs): 40 this part focuses to the Hardware Accelerator Synthesis. 35 41 It specifies how tasks must be written (C/C++ subset) and how 36 42 communication schemes must be described for coprocessor synthesis. 43 \item[Magillem framework specification] (\Smds): 44 this part specifies the fonctionnalities enabling the interactions between 45 Magillem and the core engine. 37 46 \end{description} 38 47 \itemL{6}{12}{d}{\Supmc}{Use model specification}{3:0:0} -
anr/task-4.tex
r278 r287 43 43 Release of the GAUT software that is able to read \xcoach format and to write \xcoachplus format. 44 44 \end{livrable} 45 % 46 \subtask{Adapting HAS tools to the COACH communication schemes} 47 \begin{livrable} 48 \itemL{12}{18}{x}{\Supmc}{UGH update for COACH communications}{0:2:4.0} 49 Release of the UGH software that interprets the API of task communication. 50 \itemL{12}{18}{x}{\Subs}{GAUT update for COACH communications}{0:2:4.0} 51 Release of the GAUT software that interprets the API of task communication. 52 \end{livrable} 45 53 46 54 \subtask{Coprocessor frequency adaptation} -
anr/task-5.tex
r278 r287 11 11 % 12 12 \begin{objectif} 13 This task pools the features dedicated to HPC system design. It is described on 14 figures~\ref{coach-flow} and \ref{archi-hpc}. It consists in 13 This task deals with the COACH HPC feature that consists in accelerating an existing 14 application running on a PC by migrating critical parts into a SoC implemented on an 15 FPGA plugged to the PC PCI/X bus (figures~\ref{coach-flow} and \ref{archi-hpc}). 16 It consists in: 15 17 \begin{itemize} 16 \item Providing a software tool that helps the HPC designer to find a good partition of the initial application 17 (figure~\ref{archi-hpc}). 18 \item specification of the communication schemes between the software part running on the PC and the 18 \item Specification and implementation of the communication schemes between the software part running on the PC and the 19 19 FPGA-SoC. 20 \item Implementing the communication scheme at all levels: partition help, software 21 implementation both on the PC and in the operating system of the FPGA-SoC, hardware. 22 %\item Providing support for dynamic partial reconfiguration of \xilinx FPGA in order 23 %to optimize FPGA ressource usage. 20 \item Providing a performance analysis tool helping user in the HPC partitionning (figure~\ref{archi-hpc}). 21 \item Providing support for configuration of the FPGA in order to set up the HPC environement. 24 22 \end{itemize} 25 23 … … 34 32 \begin{workpackage} 35 33 \subtask{Implementation of API between PC and FPGA-SoC} 36 This \ST deals with the COACH HPC feature that consists in accelerating an existing37 application running on a PC by migrating critical parts into a SoC implemented on an38 FPGA plugged to the PC PCI/X bus.39 The main steps and components of this \ST are:40 \begin{itemize}41 \item The definition of the communication middleware as a software API (Application42 Programing Interface) between the application part running on the PC and the43 application part running on the FPGA-SoC.44 \item A software for helping the end-user to partition applications (figure~\ref{archi-hpc}).45 This software is a library implementing the communication API with features to profile46 the partitioned application.47 \item The implementation of the communication API on the both sides (PC part and FPGA-SoC).48 \end{itemize}49 34 \begin{livrable} 50 35 \itemL{0}{6}{d}{\Sbull}{HPC communication API}{3:0:0} … … 73 58 74 59 \subtask{SystemC model of the PCI/X} 75 This \ST deals with the implementation of hardware andSystemC modules60 This \ST deals with the implementation of SystemC modules 76 61 required by the neutral architectural template for using the PCI/X IP of \altera and \xilinx. 77 62 \begin{livrable} … … 88 73 \end{livrable} 89 74 90 % \subtask This \ST consists in integrating dynamic partial reconfiguration of \xilinx FPGA in the CSG design flow. 75 \subtask{HPC environment set up} 76 91 77 % It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library. 92 % \begin{livrable} 93 % \itemL{24}{36}{x}{\Supmc}{CSG support for \ganttlf reconfiguration}{0:0:2} 94 % Modification of the CSG software to support statically reconfigurable tasks. 78 \begin{livrable} 79 \itemL{24}{36}{x}{\Stima}{Support for HPC environment set up}{0:0:2} 80 Modification of the CSG software to set-up the HPC environement: Bitsream loader. 81 \end{livrable} 95 82 % \itemL{18}{36}{x}{\Stima}{CSG module for \ganttlf dynamic reconfiguration}{0:4:12} 96 83 % This livrable is a CSG module allowing to partition the task graph along … … 118 105 % % \begin{livrable} 119 106 % % \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards. 120 % % \end{livrable}121 107 \end{workpackage} -
anr/task-7.tex
r279 r287 20 20 % 21 21 \begin{workpackage} 22 \subtask{\mustbecompleted{TITLE}} This \ST relates to the management of the WEB site and to the distribution of 23 the COACH releases. 22 \subtask{Distribution of COACH releases} 24 23 \begin{livrable} 25 \itemV{0}{6}{d}{\Supmc}{Dissemination WEB site} 26 This deliverable consists firstly in providing a WEB site (name, HTTP server 27 setup, wiki) and secondly in defining the site map and finally in writting and 28 installing the pages. 29 \itemL{6}{36}{d}{\Supmc}{Dissemination WEB site}{1:.5:.5} 30 This deliverable corresponds to the standard management of a WEB site (modifying, 31 adding, suppressing, replacing pages). 32 Especialy the user reference manuals provided in the other tasks will be published 33 on this site. The published articles will be also be installed in this site. 34 \itemL{6}{36}{d+x}{\Supmc}{Release handling}{1:.5:.5} 24 \itemL{6}{36}{d+x}{\Supmc}{Open source release}{1:.5:.5} 25 \OtherPartner{12}{36}{\Stima}{0:2:1} 35 26 This deliverable deals with the elaboration of the COACH software milestones and 36 27 final releases with their installation manuals and to publish then into the WEB 37 28 site. 38 \OtherPartner{12}{36}{\Stima}{0:2:1} 29 \itemL{6}{36}{d+x}{\Smds}{Commercial release}{1:.5:.5} 30 This deliverable deals with the elaboration of a release of COACH integrated 31 into the Magillem environment. 39 32 \end{livrable} 40 \subtask{ \mustbecompleted{TITLE}}33 \subtask{Tutorial} 41 34 \label{subtask-tutorial} 42 35 This \ST consists of making a COACH tutorial and to publish it on the public WEB … … 54 47 how a promising task graph can be obtained. 55 48 \itemV{18}{24}{d}{\Supmc}{Tutorial} 49 \OtherPartner{12}{36}{\Smds}{0:2:2} 56 50 This tutorial shows how a task can be migrated to coprocessor using HAS tools and 57 51 how FPGA-SoC can be generated and run to FPGA. This for HAS tools and and 58 architectural template available in T0+24 milestone. 52 architectural template available in T0+24 milestone.\\ 53 A part (written by \Smds) will be dedicated to the integration of COACH generated IP 54 into an IP-XACT based design flow (such as SOCKET). 59 55 \itemL{30}{36}{d}{\Supmc}{Tutorial}{2:1:1} 60 56 The final release of the tutorial. 61 57 \end{livrable} 62 \subtask{ \mustbecompleted{TITLE}}58 \subtask{Reference user manuals} 63 59 This \ST consists of making the COACH user reference manuals. 64 60 They will be published on the public WEB site. … … 74 70 the COACH project. 75 71 \OtherPartner{12}{36}{\Subs}{0:2:2} 72 \itemL{18}{36}{d}{\Smds}{Magillem framework user manual}{0:1:1} 73 This user manual describes how to use COACH within the IP-XACT based Magillem tool suite. 76 74 \end{livrable} 77 75 \end{workpackage}
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