Changeset 287 for anr/task-5.tex

Timestamp:

Dec 6, 2010, 5:26:44 PM (14 years ago)

Author:

coach

Message:

MAJ après réunion de travail Ivan, Magillem
Liste des livrables

File:

• anr/task-5.tex (modified) (5 diffs)

anr/task-5.tex

@@ -11 +11 @@
 %
 \begin{objectif}
-This task pools the features dedicated to HPC system design. It is described on
-figures~\ref{coach-flow} and \ref{archi-hpc}. It consists in
+This task deals with the COACH HPC feature that consists in accelerating an existing
+application running on a PC by migrating critical parts into a SoC implemented on an
+FPGA plugged to the PC PCI/X bus (figures~\ref{coach-flow} and \ref{archi-hpc}).
+It consists in:
 \begin{itemize}
-\item Providing a software tool that helps the HPC designer to find a good partition of the initial application
-    (figure~\ref{archi-hpc}).
-\item specification of the communication schemes between the software part running on the PC and the
+\item Specification and implementation of the communication schemes between the software part running on the PC and the
 FPGA-SoC.
-\item Implementing the communication scheme at all levels: partition help, software
-implementation both on the PC and in the operating system of the FPGA-SoC, hardware.
-%\item Providing support for dynamic partial reconfiguration of \xilinx FPGA in order
-%to optimize FPGA ressource usage.
+\item Providing a performance analysis tool helping user in the HPC partitionning (figure~\ref{archi-hpc}).
+\item Providing support for configuration of the FPGA in order to set up the HPC environement.
 \end{itemize}
 
@@ -34 +32 @@
 \begin{workpackage}
   \subtask{Implementation of API between PC and FPGA-SoC}
-    This \ST deals with the COACH HPC feature that consists in accelerating an existing
-    application running on a PC by migrating critical parts into a SoC implemented on an
-    FPGA plugged to the PC PCI/X bus.
-    The main steps and components of this \ST are:
-    \begin{itemize}
-      \item The definition of the communication middleware as a software API (Application
-        Programing Interface) between the application part running on the PC and the
-        application part running on the FPGA-SoC.
-      \item A software for helping the end-user to partition applications (figure~\ref{archi-hpc}).
-        This software is a library implementing the communication API with features to profile
-        the partitioned application.
-      \item The implementation of the communication API on the both sides (PC part and FPGA-SoC).
-    \end{itemize}
     \begin{livrable}
       \itemL{0}{6}{d}{\Sbull}{HPC communication API}{3:0:0}
@@ -73 +58 @@
 
 \subtask{SystemC model of the PCI/X}
-    This \ST deals with the implementation of hardware and SystemC modules
+    This \ST deals with the implementation of SystemC modules
     required by the neutral architectural template for using the PCI/X IP of \altera and \xilinx.
     \begin{livrable}
@@ -88 +73 @@
     \end{livrable}
 
-% \subtask This \ST consists in integrating dynamic partial reconfiguration of \xilinx FPGA in the CSG design flow.
+\subtask{HPC environment set up}
+
 % It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library.
-%     \begin{livrable}
-%     \itemL{24}{36}{x}{\Supmc}{CSG support for \ganttlf reconfiguration}{0:0:2}
-%         Modification of the CSG software to support statically reconfigurable tasks.
+     \begin{livrable}
+     \itemL{24}{36}{x}{\Stima}{Support for HPC environment set up}{0:0:2}
+      Modification of the CSG software to set-up the HPC environement: Bitsream loader.
+     \end{livrable}
 %     \itemL{18}{36}{x}{\Stima}{CSG module for \ganttlf dynamic reconfiguration}{0:4:12}
 %               This livrable is a CSG module allowing to partition the task graph along
@@ -118 +105 @@
 % %   \begin{livrable}
 % %   \itemL{0}{6}{m}{\Saltera}{HPC development boards}{0:0:0} Two PCI/X FPGA boards.
-% %   \end{livrable}
 \end{workpackage}