Changeset 29

Timestamp:

Jan 11, 2010, 8:43:20 AM (15 years ago)

Author:

coach

Message:

 

File:

• anr/task-5.tex (modified) (1 diff)

anr/task-5.tex

@@ -46 +46 @@
     architectural template for using the PCI/X IP of \altera and \xilinx.
     \begin{livrable}
-    \item{-1-VF}{0}{21}{h}{\Stima}{HPC hardwre \xilinx} A synthesizable VHDL description
+    \item{-1-VF}{0}{21}{h}{\Stima}{HPC hardware \xilinx} A synthesizable VHDL description
         of a PLB/VCI bridge.
-    \item{-1-VF}{0}{21}{h}{\Saltera}{HPC hardwre \altera} A synthesizable VHDL description
+    \item{-1-VF}{0}{21}{h}{\Saltera}{HPC hardware \altera} A synthesizable VHDL description
         of a AVALON/VCI bridge.
     \end{livrable}