Changeset 28

Timestamp:

Jan 11, 2010, 8:09:55 AM (15 years ago)

Author:

coach

Message:

 

Location:

anr

Files:

• task-0.tex (modified) (1 diff)
• task-1.tex (modified) (4 diffs)
• task-2.tex (modified) (4 diffs)
• task-3.tex (modified) (1 diff)
• task-4.tex (modified) (4 diffs)
• task-6.tex (modified) (1 diff)

anr/task-0.tex

@@ -23 +23 @@
     patners to sign it.
     \begin{livrable}
-    \item{-VF}{0}{6}{d}{\upmc}{Consortium agreement establishment} A document signed by
+    \item{-VF}{0}{6}{d}{\Supmc}{Consortium agreement establishment} A document signed by
         all the partners.
     \end{livrable}
 \item This \ST consists of the managment of deliverables.
     \begin{livrable}
-    \item{-1-VF}{0}{12}{d}{\upmc}{First progress report}
-    \item{-2-VF}{0}{24}{d}{\upmc}{Second progress report}
-    \item{-3-VF}{0}{36}{d}{\upmc}{Final report}
+    \item{-1-VF}{0}{12}{d}{\Supmc}{First progress report}
+    \item{-2-VF}{12}{24}{d}{\Supmc}{Second progress report}
+    \item{-3-VF}{24}{36}{d}{\Supmc}{Final report}
     \end{livrable}
 \item This \ST consists of the set up of the web site and iof its managment.
     \begin{livrable}
-    \item{-VF}{0}{6}{}{\upmc}{Web site setting}
+    \item{-VF}{0}{6}{}{\Supmc}{Web site setting}
     \end{livrable}
 \end{workpackage}

anr/task-1.tex

@@ -18 +18 @@
     MPSoC and its 3 targets hardware mapping).
     \begin{livrable}
-    \item{-1-V1}{0}{6}{d}{LIP6}{user manual}
+    \item{-1-V1}{0}{6}{d}{\Supmc}{user manual}
         The first milestone of the document for allowing demonstration
         \ST to start.
-    \item{-1-V1}{6}{18}{d}{LIP6}{user manual}
+    \item{-1-V1}{6}{18}{d}{\Supmc}{user manual}
         The second milestone takes into account the missing features
         the demonstrators rise.
-    \item{-1-VF}{18}{30}{d}{LIP6}{user manual}
+    \item{-1-VF}{18}{30}{d}{\Supmc}{user manual}
         Final release.
     \end{livrable}
@@ -30 +30 @@
     document listing all the COACH software components and how they cooperate.
     \begin{livrable}
-    \item{}{0}{6}{d}{LIP6}{decription of software architecture}
+    \item{}{0}{6}{d}{\Supmc}{decription of software architecture}
         It contains the software list and the data flow among them.
     \end{livrable}
 \item This \ST specifies the \xcoach format.
     \begin{livrable}
-    \item{-1-V1}{0}{6}{d x}{LIP}{specification of \xcoach format} 
+    \item{-1-V1}{0}{6}{d x}{\Slip}{specification of \xcoach format} 
         First release of the XML specification of the \xcoach format
         and its associated documentation allowing to start HLS tools development.
-    \item{-1-V2}{6}{12}{d x}{LIP}{specification of \xcoach format}
+    \item{-1-V2}{6}{12}{d x}{\Slip}{specification of \xcoach format}
         Second release of XML specification of the \xcoach format
         taking into account the corrections and modifications that the
         developers of HLS tools rise.
-    \item{-1-VF}{12}{18}{d x}{LIP}{C++ to \xcoach format}
+    \item{-1-VF}{12}{18}{d x}{\Slip}{C++ to \xcoach format}
         Release of XML specification of the \xcoach format enhanced with
         the expression of loop potential.
-    \item{-2-V1}{0}{12}{x x}{\ubs}{C++ to/from \xcoach format}
+    \item{-2-V1}{0}{12}{x x}{\Subs}{C++ to/from \xcoach format}
         The first executable generates a \xcoach description
         version \taskname-3-V1 from a C++ description of a task defined in \ST
@@ -51 +51 @@
         The second program regenerates a C description from a \xcoach
         description.
-    \item{-2-VF}{12}{18}{x x}{\ubs}{C++ to/from \xcoach format}
+    \item{-2-VF}{12}{18}{x x}{\Subs}{C++ to/from \xcoach format}
         \global\edef\STcTOxcoach{\name}
         The same programs as the former but for \xcoach format version \name-3-V2.
-    \item{-3-V1}{0}{18}{x}{LIP6}{\xcoach format to SystemC}
+    \item{-3-V1}{0}{18}{x}{\Supmc}{\xcoach format to SystemC}
         The first release of a program that translates \xcoach description to CABA
         and TLM-DT SystemC.
-    \item{-3-VF}{18}{24}{x}{LIP6}{\xcoach format to SystemC}
+    \item{-3-VF}{18}{24}{x}{\Supmc}{\xcoach format to SystemC}
         \global\edef\STxcoachTOsystemc{\name}
         The \name-3-V1 deliverable without bugs reported by the demonstrators.
-    \item{-4-V1}{0}{18}{x}{\ubs}{\xcoach format to VHDL}
+    \item{-4-V1}{0}{18}{x}{\Subs}{\xcoach format to VHDL}
         The first release of a program that translates \xcoach description to
         synthesizable VHDL description.
-    \item{-4-VF}{18}{24}{x}{\ubs}{\xcoach format to VHDL}
+    \item{-4-VF}{18}{24}{x}{\Subs}{\xcoach format to VHDL}
         \global\edef\STxcoachTOvhdl{\name}
         The \name-4-V1 deliverable without bugs reported by the demonstrators.
@@ -73 +73 @@
     and by extracting their delays. This is done by using RTL synthesis.
     \begin{livrable}
-    \item{-1-VF}{0}{6}{d}{\ubs}{macro-cell definition}
+    \item{-1-VF}{0}{6}{d}{\Subs}{macro-cell definition}
         The document define the macro cell and the file format describing them.
-    \item{-2-VF}{0}{12}{x}{\ubs}{macro-cell library generator}
+    \item{-2-VF}{0}{12}{x}{\Subs}{macro-cell library generator}
         A progam that generates automatically the characterized macro-cell library
         for a FPGA device.

anr/task-2.tex

@@ -25 +25 @@
 \item This \ST corresponds to the Coach System Generator (DSG) software.
     \begin{livrable}
-    \item{-V1}{0}{12}{x}{\upmc}{DSG} The first milestone that will allow demonstrators to
+    \item{-V1}{0}{12}{x}{\Supmc}{DSG} The first milestone that will allow demonstrators to
         start working using the COACH hardware architecture template.
-    \item{-V2}{0}{24}{x}{\upmc}{DSG} This milestone adds to DSG the support to the Xilinx
+    \item{-V2}{0}{24}{x}{\Supmc}{DSG} This milestone adds to DSG the support to the Xilinx
         and Altera architectural templates and to the enhanced communication system.
-    \item{-VF}{0}{36}{x}{\upmc}{DSG} The final release.
+    \item{-VF}{0}{36}{x}{\Supmc}{DSG} The final release.
     \end{livrable}
 \item This \ST relies to the components of the Coach architectural template.
     \begin{livrable}
-    \item{-VF}{0}{12}{x}{\upmc}{COACH architecture} The VHDL synthesizable description
+    \item{-VF}{0}{12}{x}{\Supmc}{COACH architecture} The VHDL synthesizable description
         of the SocLib MWMR, TokenRing.
     \end{livrable}
@@ -40 +40 @@
     communication schems.
     \begin{livrable}
-    \item{-V1}{0}{12}{x}{\upmc}{Mutek OS} The first milestone required by \ST T2-1-V1.
-    \item{-V2}{0}{24}{x}{\upmc}{Mutek 0S} This milestone required by \ST T2-1-V2.
-    \item{-VF}{0}{36}{x}{\upmc}{Mutek OS} The final release.
+    \item{-V1}{0}{12}{x}{\Supmc}{Mutek OS} The first milestone required by \ST T2-1-V1.
+    \item{-V2}{0}{24}{x}{\Supmc}{Mutek 0S} This milestone required by \ST T2-1-V2.
+    \item{-VF}{0}{36}{x}{\Supmc}{Mutek OS} The final release.
     \end{livrable}
 \item This \ST consists of the configuration of the SocLib DNA operating system and the
@@ -48 +48 @@
     communication schems.
     \begin{livrable}
-    \item{-V1}{0}{12}{x}{\tima}{DNA OS} The first milestone required by \ST T2-1-V1.
-    \item{-V2}{0}{24}{x}{\tima}{DNA 0S} This milestone required by \ST T2-1-V2.
-    \item{-VF}{0}{36}{x}{\tima}{DNA OS} The final release.
+    \item{-V1}{0}{12}{x}{\Stima}{DNA OS} The first milestone required by \ST T2-1-V1.
+    \item{-V2}{0}{24}{x}{\Stima}{DNA 0S} This milestone required by \ST T2-1-V2.
+    \item{-VF}{0}{36}{x}{\Stima}{DNA OS} The final release.
     \end{livrable}
 \item This \ST relies to definition and implementation of the enhanced communication
     schems usable in the definition of communicante task graph.
     \begin{livrable}
-    \item{-VF}{0}{6}{d}{\tima}{CSG user manual} A document that describes the CSG task
+    \item{-VF}{0}{6}{d}{\Stima}{CSG user manual} A document that describes the CSG task
         graph inputs (task graph, task description, communication schems). 
     \end{livrable}
@@ -61 +61 @@
     architectural template.
     \begin{livrable}
-    \item{-1-VF}{0}{18}{x}{\tima}{MWMR Altera} The VHDL synthesizable description and
+    \item{-1-VF}{0}{18}{x}{\Stima}{MWMR Altera} The VHDL synthesizable description and
         SystemC model of the MWMR with a PLB bus interface.
-    \item{-2-VF}{0}{18}{x}{\irisa}{MWMR Altera} The VHDL synthesizable description and
+    \item{-2-VF}{0}{18}{x}{\Sirisa}{MWMR Altera} The VHDL synthesizable description and
         SystemC model of the MWMR with an AVALON bus interface.
     \end{livrable}

anr/task-3.tex

@@ -13 +13 @@
     \mustbecompleted{FIXME:IRISA ........}
     \begin{livrable}
-        \item{-V1}{0}{18}{d}{\irisa}{Interation manuelle des motifs} \mustbecompleted{FIXME .....}
-        \item{-VF}{18}{24}{d}{\irisa}{Integration manuelle des motifs} \mustbecompleted{FIXME ......}
+        \item{-V1}{0}{18}{d}{\Sirisa}{Interation manuelle des motifs} \mustbecompleted{FIXME .....}
+        \item{-VF}{18}{24}{d}{\Sirisa}{Integration manuelle des motifs} \mustbecompleted{FIXME ......}
     \end{livrable}
 \item \mustbecompleted{FIXME: la liste des ST est dans wp.txt}
     \begin{livrable}
-        \item{-V1}{0}{18}{d}{\irisa}{Intégration manuelle des motifs} \mustbecompleted{FIXME ......}
+        \item{-V1}{0}{18}{d}{\Sirisa}{Intégration manuelle des motifs} \mustbecompleted{FIXME ......}
     \end{livrable}
 \end{workpackage}

anr/task-4.tex

@@ -30 +30 @@
     them by \xcoach and \xcoachplus drivers.
     \begin{livrable}
-    \item{-V1}{6}{12}{x}{\tima}{UGH integration} An executable that is able to read
+    \item{-V1}{6}{12}{x}{\Stima}{UGH integration} An executable that is able to read
         \xcoach format.
-    \item{-VF}{12}{18}{x}{\tima}{UGH integration} An executable that is able to read
+    \item{-VF}{12}{18}{x}{\Stima}{UGH integration} An executable that is able to read
         \xcoach format and to write \xcoachplus format.
     \end{livrable}
@@ -39 +39 @@
     them by \xcoach and \xcoachplus drivers.
     \begin{livrable}
-    \item{-V1}{6}{12}{x}{\tima}{GAUT integration} An executable that is able to read
+    \item{-V1}{6}{12}{x}{\Stima}{GAUT integration} An executable that is able to read
         \xcoach format.
-    \item{-VF}{12}{18}{x}{\tima}{GAUT integration} An executable that is able to read
+    \item{-VF}{12}{18}{x}{\Stima}{GAUT integration} An executable that is able to read
         \xcoach format and to write \xcoachplus format.
     \end{livrable}
@@ -48 +48 @@
     usefull enhancements
     \begin{livrable}
-    \item{-1-VF}{18}{24}{x}{\tima}{UGH enhancement 1} A UGH excutable that is able to treat
+    \item{-1-VF}{18}{24}{x}{\Stima}{UGH enhancement 1} A UGH excutable that is able to treat
         automatically data dominated sections included into a control dominated application.
-    \item{-2-VF}{21}{27}{x}{\tima}{UGH enhancement 2} A UGH executable that is able to
+    \item{-2-VF}{21}{27}{x}{\Stima}{UGH enhancement 2} A UGH executable that is able to
         generate an micro-architecture without the varaiable binding currently done by the
         designer.
-    \item{-3-VF}{18}{24}{x}{\upmc}{GAUT enhancement 1} A GAUT excutable that is able to
+    \item{-3-VF}{18}{24}{x}{\Supmc}{GAUT enhancement 1} A GAUT excutable that is able to
         \mustbecompleted{FIXME:UBS: ........}.
-    \item{-4-VF}{21}{27}{x}{\upmc}{GAUT enhancement 2} A GAUT excutable that is able to
+    \item{-4-VF}{21}{27}{x}{\Supmc}{GAUT enhancement 2} A GAUT excutable that is able to
         \mustbecompleted{FIXME:UBS: ........}.
-    \item{-5-VF}{21}{27}{x}{\upmc}{GAUT enhancement 2} A GAUT excutable that is able to
+    \item{-5-VF}{21}{27}{x}{\Supmc}{GAUT enhancement 2} A GAUT excutable that is able to
         \mustbecompleted{FIXME:UBS: ........}.
     \end{livrable}
@@ -69 +69 @@
     synthesis.
     \begin{livrable}
-    \item{-V1}{0}{6}{d}{\upmc}{frequency calibration} A document describing the set up of
+    \item{-V1}{0}{6}{d}{\Supmc}{frequency calibration} A document describing the set up of
         the coprocessor frequency calibration.
-    \item{-V2}{6}{12}{x}{\upmc}{frequency calibration} A VHDL description of hardware
+    \item{-V2}{6}{12}{x}{\Supmc}{frequency calibration} A VHDL description of hardware
         added to the coprocessor to enable the calibration.
-    \item{-V3}{12}{20}{x}{\upmc}{frequency calibration} The frequency calibration software
+    \item{-V3}{12}{20}{x}{\Supmc}{frequency calibration} The frequency calibration software
         consists of a driver in the FPGA-SoC operating system and of a control software on
         a PC.

anr/task-6.tex

@@ -18 +18 @@
     or a database management system.
     \begin{livrable}
-    \item{-V1}{0}{6}{x}{\upmc}{reference demonstrator} Choice of the demonstrator and its
+    \item{-V1}{0}{6}{x}{\Supmc}{reference demonstrator} Choice of the demonstrator and its
     implementation as a PC C/C++ program.
-    \item{-VF}{0}{12}{x}{\upmc}{partitionned reference demonstrator} The demonstrator
+    \item{-VF}{0}{12}{x}{\Supmc}{partitionned reference demonstrator} The demonstrator
     splited into 2 parts, a description as communicante task graph of the FPGA-SoC part.
     \end{livrable}