Changeset 3 for anr/body.tex

Timestamp:

Nov 26, 2009, 10:47:11 AM (15 years ago)

Author:

coach

Message:

Minor changes

File:

• anr/body.tex (modified) (7 diffs)

anr/body.tex

@@ -19 +19 @@
 due to the design and fabrication costs.
 Nowadays Field Programmable Gate Arrays (FPGA), like Virtex5 from Xilinx and Stratix4 from Altera, 
-can implement a SoC with multiple processors and several coprocessors for less than 10K euros the piece.
-In addition, High Level Synthesis (HLS) becomes more mature and allows to automize design 
-and to decrease drastically its cost in terms of man power. Thus, both FPGA and HLS tends to spread over 
-HPC for small companies targeting low volume markets.
+can implement a SoC with multiple processors and several coprocessors for less than 10K euros
+per item. In addition, High Level Synthesis (HLS) becomes more mature and allows to automate 
+design and to drastically decrease its cost in terms of man power. Thus, both FPGA and HLS 
+tend to spread over HPC for small companies targeting low volume markets.
 \par
 To get an efficient embedded system, designer has to take into account application characteristics when it 
@@ -111 +111 @@
 various application domains. The ``high end'' lines concern only FPGA with high logic capacity able 
 to implement complex systems. 
-This market is in significant expansion and is estimated to 914 M\$ in 2012.
+This market is in significant expansion and is estimated to 914\,M\$ in 2012.
 Using FPGA limits the NRE costs to design cost. This boosts the developpment of methodologies
 and tools to automize design and reduce its cost.
@@ -140 +140 @@
 segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC 
 emulation and prototyping, Mil/aero etc. HPC market size is estimated today by FPGA providers 
-to 214 M\$. 
+to 214\,M\$. 
 This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion 
 of FPGA-based solutions is limited by the flow automation. Nowadays, there are neither commercial 
@@ -149 +149 @@
 a synthesized netlist, simulation test bench and custom software library that reflect the hardware 
 configuration.
-Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors and to 
+Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors\emph{I
+(Steven) disagree : the C2H compiler bundled with SOPCBuilder does a pretty good job at this} and to
 simulate the platform at a high design level (system C). 
 In addition, SOPC Builder is proprietary and only works together with Altera's Quartus compilation
@@ -163 +164 @@
 However, this tool targets only DSP based algorithms.
 \\
-Consequently, designer developping an embedded system needs to master for example
+Consequently, designers developping an embedded system needs to master for example
 SoCLib for design exploration,
 SOPC Builde at the platform level, 
@@ -169 +170 @@
 and Quartus for design implementation.
 This requires an important tools interfacing effort and makes the design process very complex 
-and achievable only by designers skilled in various domains.
+and achievable only by designers skilled in many domains.
 COACH project integrates all these tools in the same framework masking them to the user. 
 The objective is to allow \textbf{pure software} developpers to realize embedded systems.
@@ -206 +207 @@
 extraction algorithms and datapath merging techniques to the synthesis of customized 
 ASIP processors.
+\\
+\textcolor{gris75}{Steven : Je propose de rajouter un lien avec le projet BioWic~:~on the HPC
+application side, we also hope to benefit from the experience in hardware acceleration of
+bioinformatic algorithms/workfows gathered by the CAIRN group in the context of the ANR
+BioWic project (2009-2011), so as to be able to validate the framework on 
+real-life HPC applications.}
+
 \par
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