Changeset 31

Timestamp:

Jan 12, 2010, 3:56:03 PM (15 years ago)

Author:

coach

Message:

Première révision de la section 1.
Paul

anr/section-1.tex
anr/section-3.1.tex

Location:

anr

Files:

• section-1.tex (modified) (7 diffs)
• section-3.1.tex (modified) (2 diffs)

anr/section-1.tex

@@ -1 +1 @@
 % les objectifs globaux, 
-During these last decades, the design of complex digital systems is more and more reserved 
+During the last decades, the design of complex digital systems is more and more reserved to the 
 high volume market. Indeed, the design and fabrication costs of submicronic technologies reach highs 
-due to increasing NRE (Non Recurring-Engineering) charges. The market of digital systems is about 
+due to increasing NRE (Non Recurring-Engineering) costs. The market of digital systems is about 
 4,600 M\$ today and is estimated to 5,600 M\$ in 2012.
-Digital system design has been investigated since eighties by using Applications 
-Specific Integrated Circuits (ASIC), Digital Signal Processing (DSP) and parallel computing on 
+Digital system design has been investigated since the eighties for Application 
+Specific Integrated Circuits (ASIC), Digital Signal Processors (DSP) and parallel computing on 
 multiprocessor machines or networks.  Other technologies appeared like Very Large 
 Instruction Word (VLIW) and Application Specific Instruction Processors (ASIP). 
 Unfortunatly, the ever growing applications' complexity involves higher integration of heterogeneous technologies 
-and thus requieres to design System-on-Chip (SoC) and Multi-Processors SoC (MPSoC).
-Nowadays, Field Programmable Gate Arrays (FPGA), such like Virtex5 from Xilinx
-and Stratix4 from Altera, can implement a complete SoC with multiple processors and
+and thus requieres the design of System-on-Chip (SoC) and Multi-Processors SoC (MPSoC).
+Nowadays, Field Programmable Gate Arrays (FPGA), such as the Virtex5 from Xilinx
+or the Stratix4 from Altera, can implement a complete SoC with multiple processors and
 several coprocessors for less than 10K euros per device.
 In addition, Electronic System Level (ESL) design methodologies (Virtual Prototyping, 
-Co-design, High-Level Synthesis...) become mature and allow to automate the design of digital 
-systems and to drastically decrease their cost in terms of man power.
+Co-design, High-Level Synthesis...) is now mature and allow the automation of the design of digital 
+systems and drastically decrease their cost in terms of manpower.
 Thus, coupling both FPGA and ESL methodologies will soon allow small and medium 
 enterprises (SMEs) and major companies to get into new, low and medium volume markets, 
@@ -23 +23 @@
 complex digital systems on FPGA devices.  A digital system is an application integrated into one or 
 several chips. These chips can be embedded in devices such as a personal digital assistant (PDA), 
-ambiant computing component, wireless sensor network (WSN). They can also be used on a board connected 
-to a PC to accelerate an application like in High-Performance Computing (HPC) and in High-Speed Signal 
+an ambiant computing component or a wireless sensor network (WSN). They can also be used on a board connected 
+to a PC to accelerate an application as in High-Performance Computing (HPC) or in High-Speed Signal 
 Processing (HSSP).
 
 COACH will reduce the NRE costs to the design costs (the FPGA device being only a few
-K\euro) and reduces drastically them. So one can expect that tools targeting FPGA and dedicated to software developpers
+K\euro) and drastically reduces them. If proper tools, better suited to
+softaware developers are created, one
+can expect that FPGA based devices 
 will gain market share over Multi-core CPUs and GPUs HPC based solutions.
 Moreover this market can also be boosted by small and even very small new companies
@@ -37 +39 @@
 and targeting the area of complex digital systems. This project involves the development of methodologies and 
 tools that allows an efficient design space exploration (processors, coprocessors, memories and buses or NoC) 
-of whole systems, by taking into account different application constraints (power consumption, throughput, latency...). 
+of whole systems, while taking into account different application constraints (power consumption, throughput, latency...). 
 The project will also optimize an 
 important interface, usually not taken into account, between the high-level synthesis and the implementation 
 techniques on physical targets and the associated low level tools (logic synthesis and compilation). 
-The flow will allow, from a high-level specification (written in C language), to estimate, analyze, optimize the 
-performances and finally implement a real architecture. The COACH framework will allow the designer to explore various 
-software/hardware partitioning scenario of the target application through timing and functional simulations and to 
+The design flow will allow, from a high-level specification (written in the C language), to estimate, analyze, optimize the 
+performances and then implement a real architecture. The COACH framework will allow the designer to explore various 
+software/hardware partitioning scenario for the target application through timing and functional simulations and to 
 generate automatically both the software and the synthesizable description of the hardware. 
 
@@ -55 +57 @@
 %the coprocessors, the number and the size of the FIFO communication channels 
 Basically, the 3 following architectural templates will be provided:
-A COACH architectural template based on the MIPS of the TSAR ANR project and a VCI ring bus,
-An Altera architectural template based on the NIOS and the AVALON bus,
+\begin{itemize}
+\item A COACH architectural template based on the MIPS of the TSAR ANR project and a VCI ring bus,
+\item An Altera architectural template based on the NIOS and the AVALON bus,
 %FIXME
 % The following point has to be confirmed by XILINX
 % Microblaze+OPB => ARM+Amba ???
-A Xilinx architectural template based on the MICROBLAZE and the OPB bus. 
+\item A Xilinx architectural template based on the MICROBLAZE and the OPB bus. 
+\end{itemize}
 Moreover, the specification of the application will be independant of both the template 
 architecture and the selected technology. 
-\item Design space exploration: The COACH environment will allow to select and parametrize 
-the target architecture, to define hardware/software partitioning and to profile the application. 
-For each point of design space exploration, metrics such as throughput, latency, power consumption, 
-area, memory allocation and data locality will be provided.
+\item Design space exploration: The COACH environment will allow the selection and parametrization of
+the target architecture, the definition of the hardware/software partitioning and the profiling of the application. 
+For each point in the design space, metrics such as throughput, latency, power consumption, 
+silicon area, memory allocation and data locality will be provided.
 This criteria will be evaluated by using virtual prototyping and high-level estimation methodologies.
-\item Hardware accelerators synthesis (HAS): COACH will allow to generate automatically hardware accelerators 
+\item Hardware accelerators synthesis (HAS): COACH will allow the automatic generation of hardware accelerators 
 when required. Hence, High-Level Synthesis (HLS) tools, ASIP design environement and 
 source-level transformations (loop transformations and memory optimisation) will be provided. 
-This will allow to further explore the micro-architectural design space.
+This will allow further exploration of the micro-architectural design space.
 HLS tools are sensitive to the coding style of the input specification and the domain they target (control vs. 
-data dominated). The HLS tools of COACH will support a common language and coding style to avoid engineering 
-work to the designer.
+data dominated). The HLS tools of COACH will support a common language and coding style to avoid re-engineering by the designer.
 \item Communication interface: Coach will define and implement HW/SW communication management and define APIs
 enabling communication between processors, processor/coprocessors,  FPGA and PC.
@@ -83 +86 @@
 %FIXME licence a speficier
 
-COACH will be designed to abstract the hardware as much as possible to the end user.
+The COACH tools will be designed to hide the hardware as much as possible from the end user.
 It will thus be mainly dedicated to system designers.
 
@@ -109 +112 @@
 The main steps of this project are:
 1) Definition of the user inputs: application description as set of communicating tasks, each
-task beeing described in C++ language; architectural template with its parameters; design constraints. 
+task beeing described in the C++ language; architectural template with its parameters; design constraints. 
 2) Definition of the internal \xcoach format for representing a task.
 3) Development of a GCC pluggin for generating the \xcoach representation of a C++ task.
 4) Adaptation of the existing HLS tools to read and write the \xcoach format. This will allow to 
-swap from one tool to an other one and to chain them.
-5) Modification of the Design System eXplorator DSX of the SocLib platform to let the user
+swap from one tool to another one and to chain them.
+5) Modification of the Design System eXplorator (DSX) of the SocLib platform to let the user
 explore the design space and then to generate the bitstream.
 %FIXME : a completer
@@ -126 +129 @@
 
 The COACH arhitectural templates will be freely distributed for non commercial use.
-COACH will be developped under the General Public Licence for the software tools.
+The software tools of COACH will be developped under the General Public Licence.
 

anr/section-3.1.tex

@@ -145 +145 @@
 %in the next generation of FPGA chips necessitates parallelism far beyond
 %what can be extracted from basic blocs only.
-\\
+
 %The Compsys team of LIP has built an automatic parallelizer, Syntol, which
 %handle restricted C programs -- the well known polyhedral model --, 
@@ -158 +158 @@
 %adjusting the number of threads, as a mean of exploring the 
 %area / performance tradeoff of the resulting design.
-\\
+
 %Another point is that potentially parallel programs necessarily involve
 %arrays: two operations which write to the same location must be executed