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Changeset 32
- Timestamp:
- Jan 13, 2010, 3:20:27 PM (15 years ago)
- Location:
- anr
- Files:
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- 2 edited
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section-2.1.tex (modified) (6 diffs)
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section-2.tex (modified) (1 diff)
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anr/section-2.1.tex
r18 r32 1 Microelectronic allows t o integratecomplicated functions into products, to increase their1 Microelectronic allows the integration of complicated functions into products, to increase their 2 2 commercial attractivity and to improve their competitivity. Multimedia and communication 3 sectors have taken advantage from microelectronics facilities thanks to developpment of3 sectors have taken advantage from microelectronics facilities thanks to the developpment of 4 4 design methodologies and tools for real time embedded systems. Many other sectors could 5 benefit from microelectronics if these methologies and tools are adapted to their features.5 benefit from microelectronics if these methologies and tools were adapted to their features. 6 6 The Non Recurring Engineering (NRE) costs involded in designing and manufacturing an ASIC is 7 very high. It costs several milliars of euros for IC factory and several millions to fabricate8 a specific circuit for example a conservative estimate for a 65nm ASIC project is 10 million USD.7 very high. An IC foundry costs several billions of euros and the fabrication 8 of a specific circuit costs several millions. For example a conservative estimate for a 65nm ASIC project is 10 million USD. 9 9 Consequently, it is generally unfeasible to design and fabricate ASICs in 10 10 low volumes and ICs are designed to cover a broad applications spectrum at the cost of … … 12 12 \\ 13 13 Today, FPGAs become important actors in the computational domain that was originally dominated 14 by microprocessors and ASICs. Just like microprocessors FPGA based systems can be reprogrammed15 on a per-application basis. At the same time, FPGAs offer significant performance benefits over16 microprocessors implementation for a number of applications. Although these benefits are still17 generally an order of magnitude less than equivalent ASIC implementations, low costs14 by microprocessors and ASICs. Just like microprocessors, FPGA based systems can be reprogrammed 15 on a per-application basis. At the same time, for many applications, FPGAs offer significant performance benefits over 16 microprocessors implementation. Although these benefits are still 17 generally an order of magnitude less than in equivalent ASIC implementations, low costs 18 18 (500 euros to 10K euros), fast time to market and flexibility of FPGAs make them an attractive 19 19 choice for low-to-medium volume applications. 20 20 Since their introduction in the mid eighties, FPGAs evolved from a simple, 21 low-capacity gate array t echnology to devices (Altera STRATIX III, Xilinx Virtex V) that21 low-capacity gate array to devices (Altera STRATIX III, Xilinx Virtex V) that 22 22 provide a mix of coarse-grained data path units, memory blocks, microprocessor cores, 23 23 on chip A/D conversion, and gate counts by millions. This high logic capacity allows to implement 24 24 complex systems like multi-processors platform with application dedicated coprocessors. 25 Table~\ref{fpga_market} shows the estimation of FPGA worldwide market in the next years covering 26 various application domains. The ``high end'' lines concern only FPGA with high logic capacity able 27 to implement complex systems. 25 Table~\ref{fpga_market} shows the estimation of FPGA worldwide market in the next years in 26 various application domains. The ``high end'' lines concern only FPGA with high logic capacity for complex system implementations. 28 27 This market is in significant expansion and is estimated to 914\,M\$ in 2012. 29 Using FPGA limits the NRE costs to design cost. This boosts the developpment of methodologies30 and tools to automize design and reduce its cost. 28 Using FPGA limits the NRE costs to the design cost. This boosts the developpment of of automatic design tools and methodologies. 29 31 30 \begin{table}\leavevmode\center 32 31 \begin{tabular}{|l|l|l|l|}\hline … … 52 51 for very high performance (HPC) primes over other requirements. They tend to use the highest 53 52 performing devices like Multi-core CPUs, GPUs, large FPGAs, custom ICs and the most innovative 54 architectures and algorithms. Companies show up in different "traditional" applications and market53 architectures and algorithms. These companies show up in different "traditional" applications and market 55 54 segments like computing clusters (ad-hoc), servers and storage, networking and Telecom, ASIC 56 emulation and prototyping, Mil/aero etc. HPC market size is estimated today by FPGA providers57 to214\,M\$.55 emulation and prototyping, Mil/aero etc. The HPC market size is estimated today by FPGA providers 56 at 214\,M\$. 58 57 This market is dominated by Multi-core CPUs and GPUs based solutions and the expansion 59 of FPGA-based solutions is limited by the flow automation. Nowadays, there are neither commercial60 nor freetools covering the whole design process.58 of FPGA-based solutions is limited by the lack of design flow automation. Nowadays, there are neither commercial 59 nor academic tools covering the whole design process. 61 60 For instance, with SOPC Builder from Altera, users can select and parameterize IP components 62 61 from an extensive drop-down list of communication, digital signal processor (DSP), microprocessor … … 66 65 Nevertheless, SOPC Builder does not provide any facilities to synthesize coprocessors\emph{I 67 66 (Steven) disagree : the C2H compiler bundled with SOPCBuilder does a pretty good job at this} and to 68 simulate the platform at a high design level (system 67 simulate the platform at a high design level (systemC). 69 68 In addition, SOPC Builder is proprietary and only works together with Altera's Quartus compilation 70 69 tool to implement designs on Altera devices (Stratix, Arria, Cyclone). 71 70 PICO [CITATION] and CATAPULT [CITATION] allow to synthesize coprocessors from a C++ description. 72 Nevertheless, they can only deal with data dominated applications and they do not handle the 73 platform level. 71 Nevertheless, they can only deal with data dominated applications and they do not handle the platform level. 74 72 The Xilinx System Generator for DSP [http://www.xilinx.com/tools/sysgen.htm] is a plug-in to 75 73 Simulink that enables designers to develop high-performance DSP systems for Xilinx FPGAs. … … 81 79 Consequently, designers developping an embedded system needs to master for example 82 80 SoCLib for design exploration, 83 SOPC Builde at the platform level,81 SOPC Builder at the platform level, 84 82 PICO for synthesizing the data dominated coprocessors 85 83 and Quartus for design implementation. 86 84 This requires an important tools interfacing effort and makes the design process very complex 87 85 and achievable only by designers skilled in many domains. 88 COACH project integrates all these tools in the same framework masking them to the user. 89 The objective is to allow \textbf{pure software} developpers to realize embedded systems. 86 The aim of the COACH project is to integrate all these tools in the same framework and to allow \textbf{pure software} developpers to realize embedded systems. 90 87 \par 91 88 The combination of the framework dedicated to software developpers and FPGA target, allows to gain … … 95 92 to the elimination of huge hardware investment in opposite to ASIC based solution. 96 93 \\ 97 This new market may explo se like it was done by micro-computing in eighties. This success weredue98 to the low cost of first micro-computers (compared to main frame) and the advent of high level99 programming languages that allowa high number of programmers to launch start-ups in software94 This new market may explode in the same way as the micro-computer matket in the eighties. This success was due 95 to the low cost of the first micro-processors (compared to main frames) and the advent of high level 96 programming languages which allowed a high number of programmers to launch start-ups in software 100 97 engineering. 101 98 -
anr/section-2.tex
r30 r32 1 1 The emerging complex and integrated heterogeneous embedded system platforms require 2 adequate design methods able to efficiently model, explore, analyze and design the ever complex SW3 and HWarchitectures. Future Embedded Systems suppliers, in order to meet rapidly increasing4 performance requirements linked with a pressure to lower development cost and shorten time-tomarket,5 will have to adopt new design methods and flows ableto keep pace with the increasing2 adequate design methods to efficiently model, explore, analyze and design the ever complex software 3 and hardware architectures. Future Embedded Systems suppliers, in order to meet rapidly increasing 4 performance requirements and a pressure to lower development cost and shorten time-to-market, 5 will have to adopt new design methods and flows in order to keep pace with the increasing 6 6 complexity of design problems. Such methods, addressing these challenges starting from high levels of 7 abstraction, will have to perform large solution space exploration jointly for SW and HW(possibly8 reconfigurable) , involving almost marginal design effort and offering a high predictability of results9 with respect to cost- and performance- functions.7 abstraction, will have to perform large solution space explorations both for software and (possibly 8 reconfigurable) hrdware, involving almost marginal design effort and offering a high predictability of results 9 with respect to cost- and performance- objectives. 10 10 Current design methodologies provide quite low-level abstraction capabilities. However in a few years 11 from now tens of programmable processors will be embedded in an IC with together over 100M 12 transistors adding to the complexity of the problem of architecting such systems. Taking into account 13 that the complexity of the SW part is pacing up at an even faster speed, current solutions to perform 14 design space exploration, mainly manually based, by no means do supply a performance of adequate 15 sufficiency. 11 from now tens of programmable processors will be embedded in an IC with more than 100M 12 transistors adding to the complexity of the problem of designing such systems. Taking into account 13 that the complexity of the software part is increasing at an even faster rate, current solutions for 14 design space exploration, mainly manually based, by no means do supply an adequate performance. 16 15 Consequently, there is an urgent need to leverage system level 17 16 exploration through the use of a high level specification of the application and an early design 18 space exploration step s. The first system oriented approaches are appearing, among which those19 based on C/C++ and SystemC are most popular. Such approaches can take place before and/or after20 the co-design or architecture refinement steps and target sthe design space pruning in order to fully17 space exploration step. The first system oriented approaches are appearing, among which those 18 based on C/C++ and SystemC are the most popular. Such approaches can take place before and/or after 19 the co-design or architecture refinement steps and target the design space pruning in order to fully 21 20 exploit potential solutions that meet design and application constraints (power, latency, 22 21 throughput) within the design and market timeframe. 23 22 \\ 24 23 Thus, new system-level design flows need to be developed, enabling the exploration of an application 25 independently of the implementation, thisalmost at the beginning of the design process. A24 independently of the implementation, almost at the beginning of the design process. A 26 25 fundamental element of this evolution is the definition of abstraction layers that should allow the 27 systematic re-use of SW and HWcomponents at the system level driven by performance estimation28 and analysis. I t is the context in which the COACH modeling and estimation methods combined with26 systematic re-use of software and hardware components at the system level driven by performance estimation 27 and analysis. In this context, COACH will combine modeling and estimation methods and 29 28 compilers and design space exploration techniques. This approach will cause a real breakthrough in 30 29 the embedded system design methodology, i.e. one of the radical innovations.
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