Changeset 310

Timestamp:

Jan 16, 2011, 10:02:52 AM (13 years ago)

Author:

coach

Message:

Added annexe ianswering to 2010 evaluation.

Location:

anr

Files:

• Makefile (modified) (1 diff)
• annexe-autre-participation.tex (modified) (1 diff)
• annexe-reponse.tex (added)
• anr.tex (modified) (2 diffs)
• section-2.tex (modified) (1 diff)
• section-etat-de-art.tex (modified) (7 diffs)
• section-project-description.tex (modified) (1 diff)

anr/Makefile

@@ -18 +18 @@
                         section-ressources.tex \
                         annexe-cv.tex \
-                        annexe-autre-participation.tex
+                        annexe-autre-participation.tex \
+                        annexe-reponse.tex
 
 TABLES= \

anr/annexe-autre-participation.tex

@@ -27 +27 @@
     {04/01/2008 05/31/2011}
 \autreprojettabularentry
-    {7}{Nguyen}{12}
+    {7}{Nguyen}{8}
     {Tsar, CATRENE, 695 k\euro}
     {Tera Scale ARchitecture}

anr/anr.tex

@@ -28 +28 @@
 }
 \usepackage{fancybox}
+\usepackage{marginnote}
+    \reversemarginpar
+    \renewcommand*{\raggedrightmarginnote}{\centering}
+    \renewcommand*{\marginfont}{\color{blue}\sffamily}
+    \def\note#1{\marginnote{#1}\label{note:#1}}
+    \def\seenote#1{#1 (page~\pageref{note:#1})\xspace}
 \usepackage{anr}
 
@@ -281 +287 @@
 %\end{small}
 
+\newpage\section{Prise en compte de l'évaluation 2010}
+\input{annexe-reponse.tex}
+
 \newpage\section{Letters of interest}
 \label{lettre-soutien}

anr/section-2.tex

@@ -64 +64 @@
 The COACH framework helps designer to accelerate it by migrating critical parts into a
 SoC embedded into an FPGA device plugged to the PC PCI/X bus.
-\begin{center}\begin{minipage}{.8\linewidth}\textit{
+\begin{center}\begin{minipage}{.8\linewidth}\label{HPC:definition}\textit{
 The second objective of COACH is to extend the framework for HPC applications.
 }\end{minipage}\end{center}

anr/section-etat-de-art.tex

@@ -10 +10 @@
 \end{itemize}}
 
-Our project covers several critical domains in system design in order
-to achieve high performance computing. Starting from a high level description we aim 
-at generating automatically both hardware and software components of the system.
+%Our project covers several critical domains in system design in order
+%to achieve high performance computing. Starting from a high level description we aim 
+%at generating automatically both hardware and software components of the system.
 
 \subsubsection{High Performance Computing}
+\label{soa:hpc}
 % Un marché bouffé par les archi GPGPU tel que le FERMI de NvidiaCUDA programming language
 The High-Performance Computing (HPC) world is composed of three main families of architectures:
@@ -58 +59 @@
 
 \subsubsection{System Synthesis}
+\label{soa:system:synthesis}
 Today, several solutions for system design are proposed and commercialized.
 The existing commercial or free tools do not
@@ -105 +107 @@
 
 \subsubsection{High Level Synthesis}
+\label{soa:hls}
 High Level Synthesis translates a sequential algorithmic description and a
 set of constraints (area, power, frequency, ...) to a micro-architecture at
@@ -141 +144 @@
 
 \subsubsection{Application Specific Instruction Processors}
-
+\label{soa:asip}
 ASIP (Application-Specific Instruction-Set Processor) are programmable
 processors in which both the instruction and the micro architecture have
@@ -190 +193 @@
 
 \subsubsection{Automatic Parallelization}
-
+\label{soa:automatic:parallelization}
 The problem of compiling sequential programs for parallel computers
 has been studied since the advent of the first parallel architectures 
@@ -222 +225 @@
 
 \subsubsection{SoC design flow automation using IP-XACT}
-
+\label{soa:ip-xact}
 IP-XACT is an XML based open standard defined by the Accellera consortium. 
 This non-profit organisation provides a unified set of high quality IP-XACT 
@@ -242 +245 @@
 Software layers (MEDEA+ SoftSoc project) and Accellera is reusing these results for 
 further releases.
-
+\parlf
 In IP-XACT the flow automation and data constistency is ensured by generators, which 
 are program modules that process IP-XACT XML data into something useful 

anr/section-project-description.tex

@@ -67 +67 @@
 unit).
 \parlf
+\label{HPC:howto}
 In addition to digital system design, HPC requires a supplementary
 partitioning step presented in figure~\ref{archi-hpc}. The designer