- Timestamp:
- Jan 23, 2011, 11:24:26 AM (14 years ago)
- Location:
- anr
- Files:
-
- 8 edited
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anr/annexe-autre-participation.tex
r310 r320 32 32 {\makebox{Huy-Nam} Nguyen (Bull)} 33 33 {04/01/2008 05/31/2011} 34 34 \autreprojettabularentry 35 {3}{Pétrot}{7} 36 {3DIM3, CATRENE, 741 k\euro} 37 {3D TSV Integration for MultiMedia and Mobile Applications} 38 {\makebox{Dominique} Marron (STMicroelectronics)} 39 {01/02/2009 31/01/2012} 40 \autreprojettabularentry 41 {3}{Pétrot}{4} 42 {SoftSoC, MEDEA+, 500 k\euro} 43 {Software for SoC} 44 {\makebox{Anne-Marie} Foulliard (Thales Communications)} 45 {1/03/2008 28/02/2011} 46 \autreprojettabularentry 47 {3}{Pétrot}{6} 48 {ComCas, CATRENE, 600 k\euro} 49 {Communication-centric heterogeneous Multi-Core Architectures} 50 {\makebox{Armand} Castillejo (ST-Ericsson)} 51 {01/03/2009 28/02/2012} 52 \autreprojettabularentry 53 {3}{Muller}{4} 54 {iGlance, CATRENE, 550 k\euro} 55 {Interactive Genius Look At Numerous Contemporary Events} 56 {\makebox{Michel} Imbert (STMicroelectronics)} 57 {01/07/2008 30/06/2011} 35 58 \end{autreprojettabular} -
anr/annexe-cv.tex
r319 r320 103 103 \end{itemize} 104 104 \end{cvenv} 105 \begin{cvenv} 106 {{Pétrot}{Frédéric}{44}} 107 {Professor } 108 {PhD (1994), HDR (2003)} 109 {{75}{\cite{disydent05} \cite{JerrayaPetrot} \cite{mutek} \cite{dna}}} 110 \item[Course of Lectures]\mbox{} 111 Computer Architecture, programming language, operating systems, 112 practical compilation, high-level synthesis. 113 \item[Projects]\mbox{} 114 \begin{itemize} 115 \item Hospi, SoCLib (ANR) 116 \item Medea AT403, Lomosa 117 \item OpenTLM, Sceptre (FUI) 118 \item COSY, Sprint (ESPRIT) 119 \end{itemize} 120 \begin{cvenv} 121 {{Muller}{Olivier}{30?}} 122 {Assistant Professor} 123 {PhD (2007?)} 124 {{10}} 125 \item[Course of Lectures]\mbox{} 126 Computer Architecture, assembly language programming, FPGA 127 \end{cvenv} -
anr/annexe-reponse.tex
r317 r320 139 139 Les seuls composants manquants sont les composants matériels de 140 140 communication mais ils sont incontournables pour la réalisation du projet 141 sur le les trois plateforme cible.141 sur les trois plateformes cibles. 142 142 \item[Trop gros travail de développement]\mbox{}\\ 143 143 Voir la section \ref{trop:ambitieux} ci-dessous. -
anr/anr.bib
r313 r320 117 117 118 118 @InProceedings{cosy, 119 author = { J.Y Brunel , al},119 author = { J.Y Brunel and A. San Giovanni-Vincentelli and R. Krees and W. Kruijtzer }, 120 120 title = { COSY: a methodology for system design based on reusable hardware \& software IP's}, 121 121 booktitle = { Technologies for the Information Society }, … … 865 865 } 866 866 867 867 @inproceedings{mutek, 868 author = {Fr\'ed\'eric P\'etrot and Pascal Gomez}, 869 title = {Lightweight Implementation of the POSIX Threads API for an On-Chip MIPS Multiprocessor with VCI Interconnect}, 870 booktitle = {Proceedings of the conference on Design, Automation and Test in Europe}, 871 year = {2003}, 872 isbn = {0-7695-1870-2-2}, 873 pages = {20051}, 874 publisher = {IEEE Computer Society}, 875 address_hide = {Washington, DC, USA}, 876 } 877 @inproceedings{dna, 878 Author = {Xavier Gu\'erin and Fr\'ed\'eric P\'etrot}, 879 booktitle={IEEE International Conf. on Application -specific Systems, Architectures and Processors}, 880 Title = {A {S}ystem {F}ramework for the {D}esign of {E}mbedded {S}oftware {T}argeting {H}eterogeneous {M}ulti-{C}ore {S}o{C}s}, 881 Year = {2009}, 882 pages = {153-160}, 883 } 868 884 869 885 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%% -
anr/anr.tex
r311 r320 2 2 3 3 \usepackage[french,english]{babel} 4 \usepackage[utf8 ]{inputenc}4 \usepackage[utf8x]{inputenc} 5 5 \usepackage{times} 6 6 \usepackage[T1]{fontenc} -
anr/section-consortium-people.tex
r319 r320 49 49 50 50 \peopletabularentry{\tima} 51 responsible & P\'{e}trot & Fr\'ed\'eric& professor & ... & ... & ... \\\hline 52 & Muller & Olivier & assistant professor & ... & ... & ... \\\hline 51 responsible & P\'etrot & Fr\'ed\'eric& professor & SOC HLS HPC & 12 & Architecture and micro-architecture, OS design, virtual prototyping, HLS. Participation to Task-1/2/3/5/6\\\hline 52 & Muller & Olivier & assistant professor & SOC HLS & 16 & SOC design and prototyping on FPGA \\\hline 53 & Prost-Boucle& Adrien & PhD candidate & SOC HLS & 24 & FPGA Configuration\\\hline 53 54 ... & ... & ... & ... & ... & ... & ... \\\hline 54 55 -
anr/section-ressources.tex
r317 r320 119 119 The PhD student will mainly work on the evolution of UGH HLS tool. Thus, we are looking 120 120 for a profile with strong informatic skills and good knowledge in computer architecture. 121 The post-doc will mainly work on dynamicreconfiguration and HPC. The required profile121 The post-doc will mainly work on FPGA reconfiguration and HPC. The required profile 122 122 will be more oriented on computer architecture and advanced digital design. 123 123 \parlf -
anr/task-csg.tex
r314 r320 41 41 \begin{livrable} 42 42 \itemV{6}{8}{x}{\Stima}{DNA OS} 43 The drivers required for the first CSG milestone. 43 Idenfication and Specification of the drivers required for 44 the first CSG release using a vendor neutral virtual 45 prototype. 44 46 \itemV{8}{18}{x}{\Stima}{DNA 0S} 45 The drivers required for the second CSG milestone. 47 Implementation of the identified drivers and integration in 48 the first CSG release. 46 49 \itemL{18}{33}{x}{\Stima}{DNA OS drivers for SoCLib}{6:2:2} 47 50 \OtherPartner{6}{33}{\Supmc} {.5:.5:.5} 48 \mustbecompleted{TIMA : ajouter des précisions sur le travail et ce 49 que fait upmc} 50 Final release of the DNA OS drivers. 51 Final release of the DNA OS drivers for the CSG selected IPs. 51 52 \itemL{12}{18}{x}{\Stima}{Driver ports}{0:2:0} 52 53 \OtherPartner{6}{33}{\Supmc} {0:2:0} 53 \mustbecompleted{TIMA: tima sur \xilinxcpu, UPMC sur Nios} 54 Porting of DNA OS on the NIOS2 and \xilinxcpu processors. 54 %\mustbecompleted{TIMA: tima sur \xilinxcpu, UPMC sur Nios} 55 Final port of the DNA OS on the NIOS2 and \xilinxcpu 56 processors and CSG platforms, along with the driver dependant 57 drivers. 58 \Stima will focus on the platform based on Xilinx IPs, whereas 59 \Supmc will focus on the Altera related IPs and platform. 55 60 \end{livrable} 56 61 \subtask{Implementation of CSG}
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