Changeset 319 for anr


Ignore:
Timestamp:
Jan 20, 2011, 12:50:48 PM (14 years ago)
Author:
coach
Message:

template for Christophe CV, minor language modifications

anr/annexe-cv.tex
anr/section-consortium-people.tex
anr/section-objectif.tex
anr/section-1.tex
anr/section-2.tex
anr/section-position.tex
anr/section-etat-de-art.tex
anr/section-issues.tex

Location:
anr
Files:
8 edited

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  • anr/annexe-cv.tex

    r318 r319  
    8484    \end{itemize}
    8585\end{cvenv}
     86%
     87\begin{cvenv}
     88  {{Alias}{Christophe}{33}}
     89  {Junior Researcher, INRIA}
     90  {PhD Thesis, 2005}
     91  {{%number of pubs
     92   }{%citations
     93  }}
     94  \item[Course of Lectures]\mbox{}
     95       Compilation, Architecture.
     96  \item[Projects]\mbox{}
     97    \begin{itemize}
     98       \item S2S4HLS, 2009--
     99    \end{itemize}
     100  \item[Other Work Experience]\mbox{}
     101    \begin{itemize}
     102       \item Post docs at ENS Lyon/LIP and Ohio State U ?
     103    \end{itemize}
     104\end{cvenv}

  • anr/section-1.tex

    r316 r319  
    3131such as ATOM E600C (Intel).
    3232Probably in few years, one can expect that such chips will become current and even standard
    33 general purpose CPU cores will contains a configurable area making explode the low and medium volume
    34 markets of digital systems.
     33general purpose CPU cores will contains a configurable area%
     34%paul
     35bringing an explosion in low and medium volume markets.
    3536\parlf
    3637The objective of COACH is to provide an integrated design flow for the design of

  • anr/section-2.tex

    r311 r319  
    7272unadapted to the current GPU based solutions.
    7373\parlf
    74 Coach generates SoC which is part of larger system. Thus it's important to take in account the existing industrial design flow. For this reason COACH will use the IP-XACT IEEE 1685 standard for packaging these generated SoC.
     74Coach generates SoC which is part of larger system. Thus it is important to take in account the existing industrial design flow. For this reason COACH will use the IP-XACT IEEE 1685 standard for packaging these generated SoC.
    7575\begin{center}\begin{minipage}{.8\linewidth}\textit{
    7676The third objective of COACH is to facilitate the integration of generated SoC in global system design flow.

  • anr/section-consortium-people.tex

    r315 r319  
    4444
    4545\peopletabularentry{\lip}
    46 responsible & Feautrier   & Paul        & professor           & ...         & ... & ... \\\hline
    47 ...         & ...         & ...         & ...                 & ...         & ... & ... \\\hline
    48 ...         & ...         & ...         & ...                 & ...         & ... & ... \\\hline
     46responsible & Alias       & Christophe  & junior reasearcher  & HLS         & ... & Memory management, HLS \\\hline
     47contributor & Feautrier   & Paul        & emeritus professor  & Compil.     & ... & Process scheduling and building.
     48                                                                                    Automatic Parallelization \\ \hline
    4949
    5050\peopletabularentry{\tima}

  • anr/section-etat-de-art.tex

    r315 r319  
    7878\\
    7979In the opposite, SOPC Builder~\cite{spoc-builder} from \altera and \xilinx
    80 Platform Studio XPS from \xilinx allows to describe a system, to synthesis it,
     80Platform Studio XPS from \xilinx allows to describe a system, to synthesize it,
    8181to program it into a target FPGA and to upload a software application.
    8282Both SOPC Builder and XPS, allow designers to select and parameterize components from
    … …  
    128128\item The parallelism is extracted from initial specification.
    129129To get more parallelism or to reduce the amount of required memory in the SoC, the user
    130 must re-write the algorithmic specification while there is techniques such as polyedric
     130must re-write the algorithmic specification while there are techniques such as polyedric
    131131transformations to increase the intrinsic parallelism,
    132132\item While they support limited loop transformations like loop unrolling and loop
    133 pipelining, current HLS tools do not provide support for design space exploration neither
    134 through automatic loop transformations nor through memory mapping,
     133pipelining, current HLS tools do not provide support for design space exploration, either
     134through automatic loop transformations or through memory mapping,
    135135\item Despite having the same input language (C/C++), they are sensitive to the style in
    136 which the algorithm dis written. Consequently, engineering work is required to swap from
     136which the algorithm is written. Consequently, engineering work is required to swap from
    137137a tool to another,
    138138\item They do not respect accurately the frequency constraint when they target an FPGA device.
    … …  
    146146\label{soa:asip}
    147147ASIP (Application-Specific Instruction-Set Processor) are programmable
    148 processors in which both the instruction and the micro architecture have
     148processors in which both the instruction set and the micro architecture have
    149149been tailored to a given application domain or to a
    150150specific application.  This specialization usually offers a good compromise
    … …  
    220220tool for many other optimization, like memory reduction and locality
    221221improvement. Another point is
    222 that the polyhedral domain \emph{stricto sensu} applies only to
     222that the polyhedral model \emph{stricto sensu} applies only to
    223223very regular programs. Its extension to more general programs is
    224224an active research subject.
    … …  
    245245are members of the consortium and the board is incorporating top actors
    246246(STM, NXP, TI, ARM, FREESCALE, LSI, Mentor, Synopsys and Cadence), ensuring the
    247 wide adoption by industry. Initiatives have already work for extending this standard
     247wide adoption by industry. Initiatives have already% work for (paul)
     248attempted to extend this standard
    248249to AMS IPs packaging domain (MEDEA+ Beyond Dreams Project) and to Hardware Dependent
    249250Software layers (MEDEA+ SoftSoc project) and Accellera is reusing these results for

  • anr/section-issues.tex

    r312 r319  
    3333thanks to the developpment of design methodologies and tools for embedded systems.
    3434Unfortunately, the Non Recurring Engineering (NRE) costs involded in the design
    35 and manufacturing ASICs is very high.
     35and manufacturing of ASICs is very high.
    3636An IC foundry costs several billions of euros and the fabrication of a specific circuit
    3737costs several millions. For example a conservative estimate for a 65nm ASIC project is 10
    38 million USD.C onsequently, it is more and more unaffordable to design and fabricate ASICs for low and medium
     38million USD. Consequently, it is more and more unaffordable to design and fabricate ASICs for low and medium
    3939volume markets and the new trend for building the new generation products will be multi processors SoCs and programmable logic for co-processsing.
    4040\\
    4141According to a market survey (J-M. Chery, CTO ST Microelectronics at European NanoelectronicsForum 2010), the global growth is 30 Billons\$ between 2009-2013 for multimedia and communication sectors; this is 6 times more than all other domains like security, home automation, health.
    42 The predominance of market of multimedia and communication sectors results in the fact that they are mainly mass market.
     42The predominance%paul
     43the multimedia and communication sectors
     44%results paul
     45are due to their being predominently a mass market.
    4346%
    4447\subsubsection*{FPGAs and Embedded Systems}
    … …  
    8487\subsubsection*{COACH's contribution to this evolution}
    8588Nowadays, there are no commercial or academic tools covering the whole design flow
    86 from the system level specification to the bitstream generation neither for embedded system design
    87 nor for HPC.
     89from the system level specification to the bitstream generation, either for embedded system design
     90or for HPC.
    8891\begin{center}\begin{minipage}{.9\linewidth}\textit{
    8992The aim of the COACH project is to integrate all these design steps into a single design framework
    … …  
    106109to launch start-ups in software engineering.
    107110\\
    108 So this may increase the total amount of engineers working in this domain: today in France the total is only 26,000 in which 16,000 in big companies \cite{rapport-ministere}.
     111So this may increase the total%amount (paul)
     112number of engineers working in this domain: today in France the total is only 26,000 of which 16,000 are in big companies \cite{rapport-ministere}.

  • anr/section-objectif.tex

    r313 r319  
    1212The design steps are presented figure~\ref{coach-flow}.
    1313The end-user input is
    14 either a HPC application (an application running on a PC that must be accelerate),
     14either a HPC application (an application running on a PC that must be accelerated),
    1515or an embedded application (a standalone application),
    1616or a  sub-system application of a larger design.
    … …  
    7474    and the HLS tools of COACH will support a common language and coding style
    7575    to avoid re-engineering by the designer.
    76     COACH will provide a tool which will automatically explore the micro-architectural
    77     design space of coprocessor.
     76    COACH will provide a tool which will automatically explore the%paul
     77     coprocessor micro-architectural design space.
    7878\item[\textit{High-level code transformation}]:
    7979    COACH will allow to optimize the memory usage, to enhance the parallelism through

  • anr/section-position.tex

    r315 r319  
    2727environment, including communication middleware and tools to support
    2828developers in the production of embedded software, through all phases of the software lifecycle,
    29 from requirements analysis downto deployment and maintenance.
     29from requirements analysis down to deployment and maintenance.
    3030More specifically, COACH focuses on:
    3131\begin{itemize}
    … …  
    146146    to it since 2003 and Magillem tool suite is used for its validation. Magillem is used in
    147147    industrial production flows of ST, NXP, TI, Qualcomm, and system integrators like Thales,
    148     Astrium, Thomson, etc. what guarantees a strong alignement on customers needs and enhance results exploitation.
     148    Astrium, Thomson, etc. This guarantees a strong alignement on customers needs and enhanced results exploitation.
    149149
    150150\end{itemize}
    … …  
    152152\subsubsection*{Relevance to the call axis}
    153153This project answer to the global statement of the call "INGENIERIE NUMERIQUE ET SECURITE (INS)" by proposing
    154 methods and tools for the design of application to be ran on platforms of the next generation. Results will be gained in term of productivity,
     154methods and tools for the design of application to be run on platforms of the next generation. Results will be gained in term of productivity,
    155155time-to-market (automation and code generation) and safety (management of high level sepcifications down to implementation).
    156156In this call, the COACH project totally fulfills the objectives of the axis 2 "METHODES,
    … …  
    161161based on IP cores (memory, peripherals...),
    162162running Embedded Software, as well as an Operating System with associated middleware and
    163 API and using hardware accelerator automatically generated. It will also permit to use
     163API and using automatically generated hardware accelerators. It will also permit to use
    164164efficiently different dynamic system management techniques and re-configuration mechanisms.
    165165The results will be tailored in order to be integrated in standard design flow of critical systems.
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