Changeset 33


Ignore:
Timestamp:
Jan 14, 2010, 5:31:54 PM (15 years ago)
Author:
coach
Message:

Paul: des petites améliorations
M anr/section-3.2.tex
M anr/section-4.1.tex

Location:
anr
Files:
2 edited

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  • anr/section-3.2.tex

    r24 r33  
    11% les objectifs scientifiques/techniques du projet.
    2 The objectives of COACH project are to develop a complete framework to HPC
     2The objectives of the COACH project are to develop a complete framework to HPC
    33(accelerating solutions for existing software applications) and embedded
    44applications (implementing an application on a low power standalone
    … …  
    1010\begin{description}
    1111\item[HPC setup] Here the user splits the application into 2 parts: the host application
    12 which remains on PC and the SoC application which migrates on SoC.
    13 The framework provides a simulation model allowing to evaluate the partitioning.
     12which remains on a PC and the SoC application which migrates into a SoC.
     13The framework provides a simulation model which allows an evaluation of the partitioning.
    1414\item[SoC design] In this phase,
    15 The user can obtain simulators at different abstraction levels of the SoC by giving to COACH framework
    16 a SoC description. 
     15The user can obtain simulators for the SoC at different abstraction levels by giving to the COACH framework a SoC description. 
    1716This description consists of a process network corresponding to the SoC application,
    1817an OS, an instance of a generic hardware platform
    … …  
    2120XXXpeci (the process runs on a SoC processor enhanced with dedicated instructions),
    2221and hardware (the process runs into a coprocessor generated by HLS and plugged on the SoC bus).
    23 \item[Application compilation] Once SoC description is validated, COACH generates automatically
    24 an FPGA bitstream containing the hardware platform with SoC application software and
     22\item[Application compilation] Once the SoC description is validated, COACH generates automatically
     23an FPGA bitstream containing the hardware platform with the SoC application software and
    2524an executable containing the host application. The user can launch the application by
    26 loading the bitstream on FPGA and running the executable on PC.
     25loading the bitstream on an FPGA and running the executable on PC.
    2726\end{description}
    2827 
    … …  
    3130The main scientific contribution of the project is to unify various synthesis techniques
    3231(same input and output formats) allowing the user to swap without engineering effort
    33 from one to an other and even to chain them, for example, to run polyedric transformation
    34 before synthesis.
     32from one to another and even to chain them. for instance, it will be possible to run polyedric transformations before synthesis.
    3533Another advantage of this framework is to provide different abstraction levels from
    3634a single description.
    … …  
    4442\begin{itemize}
    4543\item The main problem in HPC is the communication between the PC and the SoC.
    46 This problem has 2 aspects. The first one is the efficiency. The second is to
    47 eliminate enginnering effort to implement it at different abstract levels.
    48 \item COACH design flow has a top-down approach. In the such case,
    49 the required performance of a coprocessor (run frequency, maximum cycles for
     44This problem has 2 aspects. The first one is the run-time efficiency. The second is its engineering  cost, especially if one want to refine an implementation
     45at several abstract levels.
     46\item The COACH design flow has a top-down approach. In such a case,
     47the required performance of a coprocessor (clock frequency, maximum cycles for
    5048a given computation, power consumption, etc) are imposed by the other system
    5149components. The challenge is to allow user to control accurately the synthesis
    52 process. For instance, the run frequency must not be a result of the RTL synthesis
     50process. For instance, the clock frequency must not be a result of the RTL synthesis
    5351but a strict synthesis constraint.
    5452\item HLS tools are sensitive to the style in which the algorithm is written.
    … …  
    6664The challenge is to identify the coarse grained parallelism and to generate,
    6765from a sequential algorithm, coprocessor containing multiple communicating
    68 tasks (data-paths and FSMs).
     66tasks (data-paths and FSMs). To this aim, one may adapt techniques which
     67were developed in the 1990 for the construction of distributed programs.
     68However, in the context of HLS, there are still several original problems
     69to be solved, mainly to do with the construction of FIFO communication
     70channels and with memory optimization.
     71
    6972\end{itemize}
    7073
    … …  
    7376%fin de projet.
    7477The main result is the framework. It is composed concretely of:
    75 2 HPC communication shemes with their implementation,
     782 HPC communication schemes with their implementation,
    76795 HLS tools (control dominated HLS, data dominated HLS, Coarse grained HLS,
    7780Memory optimisation HLS and ASIP),

  • anr/section-4.1.tex

    r23 r33  
    1212\end{figure}
    1313%
    14 The figures~\ref{archi-csg}, \ref{archi-hls} and \ref{archi-hpc}
    15 summarize the software architecture of COACH framework we plan to develop.
     14Figures~\ref{archi-csg}, \ref{archi-hls} and \ref{archi-hpc}
     15summarize the software architecture of the COACH framework we plan to develop.
    1616In figures, the dotted boxes are the softwares or formats that COACH
    1717has to provide.
    … …  
    4848The input is a single task of the process network. The HAS tools do not work
    4949directly on the C++ task description but on an internal format called
    50 \xcoach generated by a the GNU C compiler (GCC) tainted by a COACH
     50\xcoach generated by a the GNU C compiler (GCC)
     51%Paul: ``tainted'' ça ve dire ``souillé''. Qu'est-ce que tu veux dire
     52%exactement: piloté, modifié ....?
     53tainted by a COACH
    5154driver. This allows on the one hand to insure that all the tools will
    5255accept the same C++ description and on the other hand to make possible
    … …  
    6972is done through \verb!CSG! (figure~\ref{archi-csg}).
    7073\vspace*{.75ex}\par
    71 The project is splitted into 8 tasks numbered from 0 to 7.
     74The project is split into 8 tasks numbered from 0 to 7.
    7275The first task (task 0) is the project management, the last one (task 7) is
    7376the dissemination the other task are listed below:
    … …  
    9598    both PC and FPGA-SoC sides, the hardware communication components.
    9699\item\textbf{Demonstrators:}
    97     This task groups the demostrators of the COACH project.
     100    This task groups the demonstrators of the COACH project.
    98101    \mustbecompleted{FIXME}
    99102\end{enumerate}
    … …  
    122125\item $T7$ and $T0$ respectively depends on and impacts all the other tasks.
    123126\end{itemize}
    124 So this organisation offers enough robustness for insure the success of the
    125 project except for the specification task $T1$. However, the partners meet
    126 10 times (a one day meeting per month) during the last years to prepare the
    127 specification and the project proposal.
     127This organisation offers enough robustness to insure the success of the
     128project except for the specification task $T1$.
     129
     130The only critical task in this chart is T1.
     131
     132However, the partners met
     13310 times (a one day meeting per month) during the last year to prepare the
     134specification and the project proposal. This gives us a degree of confidence
     135that T1 will be completed in time.
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