Changeset 335 for anr/task-frontend.tex

Timestamp:

Jan 28, 2011, 5:22:40 PM (14 years ago)

Author:

coach

Message:

Mise à jour INRIA Rennes - 28 janv

File:

• anr/task-frontend.tex (modified) (3 diffs)

anr/task-frontend.tex

@@ -1 +1 @@
 \begin{taskinfo}
 \let\LIP\leader
-\let\IRISA\enable
+\let\INRIA\enable
 \let\UBS\enable
 \let\UPMC\enable
@@ -27 +27 @@
   instructions definitions along with their occurrence in the application.
     \begin{livrable}
-      \itemV{0}{18}{x}{\Sirisa}{ASIP compilation flow}
+      \itemV{0}{12}{x}{\Sinria}{ASIP compilation flow}
         In this first version of the software, the computations patterns corresponding to
         custom instructions are specified by the user, and then automatically extracted (when
         beneficial) from the application intermediate representation. 
-      \itemL{18}{27}{x}{\Sirisa}{ASIP compilation flow}{0:6:3}
+      \itemL{12}{27}{x}{\Sinria}{ASIP compilation flow}{4:4:3}
         In this second version, the software will also be able to automatically identify 
         interesting pattern candidates in the application code, and use them as custom 
@@ -43 +43 @@
  of the architecture, along with its architectural extensions 
     \begin{livrable}
-      \itemV{0}{12}{x}{\Sirisa}{SystemC for extensible MIPS }
+      \itemV{0}{12}{x}{\Sinria}{SystemC for extensible MIPS }
       { A SystemC simulation model for a simple extensible MIPS architectural template }
-      \itemL{12}{20}{x}{\Sirisa}{SystemC for extensible MIPS}{2:3:0}
+      \itemL{12}{27}{x}{\Sinria}{SystemC for extensible MIPS}{3:3:0}
       {A SystemC simulation model for an extensible MIPS with a tight architectural integration of
       its instruction set extensions}
-      \itemV{3}{18}{h}{\Sirisa}{VHDL for an extensible MIPS}
+      \itemV{3}{18}{h}{\Sinria}{VHDL for an extensible MIPS}
       {A synthesizable VHDL model for a simple extensible MIPS architectural template}
-      \itemL{18}{27}{h}{\Sirisa}{VHDL for extensible MIPS}{9:9:3}
+      \itemL{18}{27}{h}{\Sinria}{VHDL for extensible MIPS}{6:6.5:3}
       {A synthesizable VHDL model for an extensible MIPS with a tight architectural integration of
       its instruction set extensions}
-      \itemL{27}{36}{d}{\Sirisa}{Evaluation report }{0:0:2}
+      \itemL{27}{36}{d}{\Sinria}{Evaluation report }{0:0:2}
       {An evaluation report with quantitative analysis of the performance/area trade-off induced by
       the different approaches}