Changeset 59 for anr

Timestamp:

Feb 2, 2010, 3:06:02 AM (15 years ago)

Author:

coach

Message:

IA: renumerotation des taches

Location:

anr

Files:

• anr.sty (modified) (1 diff)
• anr.tex (modified) (1 diff)
• gantt.l (modified) (6 diffs)
• task-0.tex (modified) (1 diff)
• task-2.tex (modified) (1 diff)
• task-5.tex (modified) (3 diffs)

anr/anr.sty

@@ -81 +81 @@
 
 %%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
-\newcount\taskcnt\taskcnt=-1
+\newcount\taskcnt\taskcnt=0
 \newcount\subtaskcnt
 \newcount\livrablecnt

anr/anr.tex

@@ -203 +203 @@
 \end{itemize}}
 
-\subsubsection{Task 0: \textit{Project management}}
+\subsubsection{Task 1: \textit{Project management}}
 \input{task-0}
 
-\subsubsection{Task 1: \textit{\Backbone}}
+\subsubsection{Task 2: \textit{\Backbone}}
 \input{task-1}
 
-\subsubsection{Task 2: \textit{System generation}}
+\subsubsection{Task 3: \textit{System generation}}
 \input{task-2}
 
-\subsubsection{Task 3: \textit{HAS front-end}}
+\subsubsection{Task 4: \textit{HAS front-end}}
 \input{task-3}
 
-\subsubsection{Task 4: \textit{HAS back-end}}
+\subsubsection{Task 5: \textit{HAS back-end}}
 \input{task-4}
 
-\subsubsection{Task 5: \textit{PC/FPGA communication middleware}}
+\subsubsection{Task 6: \textit{PC/FPGA communication middleware}}
 \input{task-5}
 
-\subsubsection{Task 6: \textit{Industrial demonstrators}}
+\subsubsection{Task 7: \textit{Industrial demonstrators}}
 \input{task-6}
 

anr/gantt.l

@@ -29 +29 @@
 
 char* task_names[] = {
+    0,
     "Project management",
     "Backbone infrastructure",
@@ -39 +40 @@
     0
 };
-struct partner_def { char *key, *name, *file; } partner_table[] = {
-    { "UNKNOW", "relax",   0,                 },
-    { "irisa",  "irisa",   "table_irisa.tex"  },
-    { "lip",    "lip",     "table_lip.tex"    },
-    { "tima",   "tima",    "table_tima.tex"   },
-    { "ubs",    "ubs",     "table_ubs.tex"    },
-    { "upmc",   "upmc",    "table_upmc.tex"   },
-    { "altera", "altera",  "table_altera.tex" },
-    { "xilinx", "xilinx",  "table_xilinx.tex" },
-    { "bull",   "bull",    "table_bull.tex"   },
-    { "thales", "thales",  "table_thales.tex" },
-    { "zied",   "zied",    "table_zied.tex"   },
-    { "navtel", "navtel",  "table_navtel.tex" },
-    { 0,        0,         0                  },
+struct partner_def { char *key, *name, *fnfull, *fnshort; } partner_table[] = {
+    { "UNKNOW" ,"relax"  ,0                       ,0                        },
+    { "irisa"  ,"irisa"  ,"table_irisa_full.tex"  ,"table_irisa_short.tex"  },
+    { "lip"    ,"lip"    ,"table_lip_full.tex"    ,"table_lip_short.tex"    },
+    { "tima"   ,"tima"   ,"table_tima_full.tex"   ,"table_tima_short.tex"   },
+    { "ubs"    ,"ubs"    ,"table_ubs_full.tex"    ,"table_ubs_short.tex"    },
+    { "upmc"   ,"upmc"   ,"table_upmc_full.tex"   ,"table_upmc_short.tex"   },
+    { "altera" ,"altera" ,"table_altera_full.tex" ,"table_altera_short.tex" },
+    { "xilinx" ,"xilinx" ,"table_xilinx_full.tex" ,"table_xilinx_short.tex" },
+    { "bull"   ,"bull"   ,"table_bull_full.tex"   ,"table_bull_short.tex"   },
+    { "thales" ,"thales" ,"table_thales_full.tex" ,"table_thales_short.tex" },
+    { "zied"   ,"zied"   ,"table_zied_full.tex"   ,"table_zied_short.tex"   },
+    { "navtel" ,"navtel" ,"table_navtel_full.tex" ,"table_navtel_short.tex" },
+    { 0        ,0        ,0                       ,0                        },
 };
 
@@ -612 +613 @@
 }
 
-void do_partner_table(int partner)
+void do_partner_table_full(int partner)
 {
     struct partner_def* part = partner_table+partner;
-    if ( (curr->os=fopen(part->file,"w"))==0 ) {
-        fprintf(stderr,"can not open %s file for writing.\n",part->file);
-        fprintf(stderr,"generation of %s partner table is skipped.\n",part->file);
+    if ( (curr->os=fopen(part->fnfull,"w"))==0 ) {
+        fprintf(stderr,"can not open %s file for writing.\n",part->fnfull);
+        fprintf(stderr,"generation of %s partner table is skipped.\n",part->fnfull);
         return;
     }
@@ -674 +675 @@
     }
     if ( an!=(an1+an2+an3) ) {
-        fprintf(stderr,"bad computation in %s table.\n",part->file);
+        fprintf(stderr,"bad computation in %s table.\n",part->fnfull);
     }
     fprintf(curr->os,"\\hline\n");
@@ -685 +686 @@
 }
 
+void do_partner_table_short(int partner)
+{
+    struct partner_def* part = partner_table+partner;
+    if ( (curr->os=fopen(part->fnshort,"w"))==0 ) {
+        fprintf(stderr,"can not open %s file for writing.\n",part->fnshort);
+        fprintf(stderr,"generation of %s partner table is skipped.\n",part->fnshort);
+        return;
+    }
+    fprintf(curr->os,"\\begin{center}\\begin{small}\\begin{tabular}{|c|l||r|r|r||r|}\\hline\n");
+    fprintf(curr->os,
+        " & title & \\multicolumn{3}{c||}{years } & total \\\\\\cline{3-5}\n");
+    fprintf(curr->os,
+        " &       & \\multicolumn{1}{c|}{1} & \\multicolumn{1}{c|}{2} & "
+                    "\\multicolumn{1}{c||}{3} &  \\\\\\hline\\hline\n");
+    int tn,stn,dn,v=0;
+    double an1=0,an2=0,an3=0,an=0;
+    double tsk1,tsk2,tsk3,tsk;
+    int newlineadded=1;
+    for (tn=0 ; tn<T_MAX ; tn++) {
+        if (curr->ls[tn][0][0][0]==0) break;
+                tsk1=tsk2=tsk3=tsk=0;
+        for (stn=0; stn<S_MAX; stn++) {
+            for (dn=0; dn<D_MAX; dn++) {
+                Tlivrable* top=curr->ls[tn][stn][dn][v];
+                if (top==0) continue;
+                Tlivrable* last=top->vers[top->nbvers-1];
+                if (last->partner!=partner) continue;
+                double sum1,sum2,sum3,sum=0;
+                sum1 = last->hman[0]; sum +=sum1;
+                sum2 = last->hman[1]; sum +=sum2;
+                sum3 = last->hman[2]; sum +=sum3;
+                an1 += sum1 ; tsk1 += sum1 ;
+                an2 += sum2 ; tsk2 += sum2 ;
+                an3 += sum3 ; tsk3 += sum3 ;
+                an  += sum  ; tsk  += sum  ;
+                newlineadded=0;
+                char label[1000];
+                gen_label_base(label,last);
+                if ( (sum1!=0 && sum1>last->nbma[0] ) || (sum1==0 && last->nbma[0]!=0) )
+                    fprintf(stderr,"ERROR: %s:%s probleme sur l'an 1 (in table=%2.1f, in gantt=%2.1f\n",
+                        part->name,label,sum1,last->nbma[0]);
+                if ( (sum2!=0 && sum2>last->nbma[1]) || (sum2==0 && last->nbma[1]!=0) )
+                    fprintf(stderr,"ERROR: %s:%s probleme sur l'an 2 (in table=%2.1f, in gantt=%2.1f\n",
+                        part->name,label,sum2,last->nbma[1]);
+                if ( (sum3!=0 && sum3>last->nbma[2]) || (sum3==0 && last->nbma[2]!=0) )
+                    fprintf(stderr,"ERROR: %s:%s probleme sur l'an 3 (in table=%2.1f, in gantt=%2.1f\n",
+                        part->name,label,sum3,last->nbma[2]);
+            }
+        }
+                if (tsk!=0)
+        fprintf(curr->os,"Task-%d & %s & %2.1f & %2.1f & %2.1f & %2.1f \\\\\\hline\n",
+            curr->ls[tn][0][0][0]->tn,
+            task_names[curr->ls[tn][0][0][0]->tn],tsk1,tsk2,tsk3,tsk);
+                
+    }
+    if ( an!=(an1+an2+an3) ) {
+        fprintf(stderr,"bad computation in %s table.\n",part->fnshort);
+    }
+    fprintf(curr->os,"\\hline\n");
+    fprintf(curr->os," & %s &  %2.1f & %2.1f & %2.1f & %2.1f \\\\\\hline\n",
+            "total",an1,an2,an3,an);
+
+    fprintf(curr->os,"\\end{tabular}\\end{small}\\end{center}\n");
+    fclose(curr->os);
+    curr->os=0;
+}
+
 int main()
 {
-    int tnplus[10] = { 0, 6, 7, -1 };
-    int tnmoins[10] = { 0, 6, 7, -1 };
+    int tnplus[10] = { 1, 7, 8, -1 };
+    int tnmoins[10] = { 1, 7, 8, -1 };
 
     yylex();
@@ -700 +768 @@
     prepare2(curr);
     prepare3(curr);
-    do_partner_table(4);
-    do_partner_table(5);
+    do_partner_table_full(4); do_partner_table_short(4);
+    do_partner_table_full(5); do_partner_table_short(5);
 
     return 0;

anr/task-0.tex

@@ -29 +29 @@
     organization of the project at all the levels.
     \begin{livrable}
-      \itemL{0}{12}{d}{\Supmc}{First progress report}{1:0:0}
-      \itemL{12}{24}{d}{\Supmc}{Second progress report}{0:1:0}
-      \itemL{24}{36}{d}{\Supmc}{Final report}{0:0:1}
-      \itemL{0}{36}{}{\Supmc}{Global management}{1:1:1}
+      \itemL{0}{36}{d}{\Supmc}{Global management}{1:1:1}
         This deliverable corresponds to the global management of the project at all the
         levels: progress monitoring, record keeping, meeting organization, review
-        organization.
+        organization, the writting of the 3 review reports.
     \end{livrable}
   \item This \ST consists of the project management at the partner level.

anr/task-2.tex

@@ -38 +38 @@
         This milestone extends CSG (\csgPrototypingOnly) to
         FPGA-SoC generation for the XILINX and ALTERA architectural template.
-    \itemL{24}{36}{x}{\Supmc}{CSG}{6:6:5}
+    \itemL{24}{36}{x}{\Supmc}{CSG}{6:6:6}
         Maintenance work of CSG.
     \end{livrable}

anr/task-5.tex

@@ -26 +26 @@
 This will allow us at least to be inspired by GPU communication schemes and may be to reuse
 parts of the GPU softwares.
-
 
 \end{objectif}
@@ -63 +62 @@
         Maintenance work of HPC API for both Linux PC and MUTEK OS.
     \end{livrable}
-\item This \ST deals with the implementation of hardware required by the COACH
-    architectural template for using the PCI/X IP of \altera and \xilinx.
+\item This \ST deals with the implementation of hardware and SystemC modules
+    required by the COACH architectural template for using the PCI/X IP of \altera and \xilinx.
     \begin{livrable}
     \itemL{9}{18}{h}{\Stima}{HPC hardware \xilinx}{3:9:0}
@@ -72 +71 @@
         \setMacroInAuxFile{hpcAvalonBridge}
         The synthesizable VHDL description of an AVALON/VCI bridge and its corresponding SystemC model.
+    \itemL{9}{24}{h}{\Supmc}{PCI/X traffic generator}{1:1:0}
+        The SystemC description of a component that generates PCI/X traffic. It is
+        required to prototype FPGA-SoC dedicated to HPC.
     \end{livrable}
+
 \item This \ST consists in integrating dynamic partial reconfiguration of \xilinx FPGA in the CSG design flow.
 It also includes appropriate SoC-FPGA OS drivers and a modification of the profiling library.
-
     \begin{livrable}
-    \itemL{18}{36}{x}{\Stima}{CSG support for \ganttlf dynamic reconfiguration}{0:8:12}
-        Extension of the \xilinx architectural template ({\csgAllArch})
-in order to integrate dynamic partial reconfiguration regions.
-Modification of CSG software to support the extended \xilinx template.
+    \itemL{18}{36}{x}{\Supmc}{CSG support for \ganttlf dynamic reconfiguration}{0:0:2}
+        Extension of the \xilinx architectural template ({\csgAllArch}) in order to
+        integrate dynamic partial reconfiguration regions.
+        Modification of CSG software to support the extended \xilinx template.
     \itemL{18}{30}{x}{\Stima}{dynamic reconfiguration \ganttlf DNA drivers}{0:2:3}
         \setMacroInAuxFile{hpcDynconfDriver}
-        The drivers required by the DNA OS in order to manage dynamic partial reconfiguration inside the SoC-FPGA.
+            The drivers required by the DNA OS in order to manage dynamic partial
+        reconfiguration inside the SoC-FPGA.
     \itemL{30}{36}{x}{\Supmc}{dynamic reconfiguration \ganttlf MUTEK drivers}{0:0:1}
         Port of the {\hpcDynconfDriver} drivers on the MUTEK OS.
     \itemL{24}{36}{x}{\Stima}{HPC profiler for \ganttlf dynamic reconfiguration}{0:0:6}
-Extension of the HPC partionning helper in order to integrate dynamic partial reconfiguration dedicated features
-(reconfiguration time of regions, variable number of coprocessors)
-\end{livrable}
+        Extension of the HPC partionning helper in order to integrate dynamic partial
+        reconfiguration dedicated features (reconfiguration time of regions, variable
+        number of coprocessors).
+    \end{livrable}
 \item This \ST is the delivery of 2 PCI/X \mustbecompleted{FIXME: Stratix4} FPGA board
     with its PCI/X IP. These boards are dedicated to the COACH HPC development.