Changeset 93 for anr/section-3.1.tex

Timestamp:

Feb 4, 2010, 7:14:55 PM (14 years ago)

Author:

coach

Message:

Fixed anr.bib with most missing references

File:

• anr/section-3.1.tex (modified) (3 diffs)

anr/section-3.1.tex

@@ -119 +119 @@
 difficult task, since it involves designing both a micro-architecture and a
 compiler for this architecture. Besides, to our knowledge, there is still
-no available open-source design flow\footnote{There are commercial tools
-such a } for ASIP design even if such a tool would be valuable in the
+no available open-source design flow for ASIP design even if such a tool
+ would be valuable in the
 context of a System Level design exploration tool.
 \par
@@ -128 +128 @@
 only a small fraction of the architecture has to be specialized}, and help ASIP
 designers to focus on compilers, for which there are still many open
-problems\cite{CODES04,FPGA08}.
+problems\cite{ARC08}.
 This approach however has a strong weakness, since it also significantly reduces 
 opportunities for achieving good seedups (most speedup remain between 1.5x and 
@@ -138 +138 @@
 %performing efficient instruction selection and/or storage resource (register) 
 %allocation \cite{FPGA08}).  
-To cope with this issue, recent approaches~\cite{DAC09,DAC08} advocate the use of 
+To cope with this issue, recent approaches~\cite{DAC09,CODES08,TVLSI06} advocate the use of 
 micro-architectural ISE models in which the coupling between the processor micro-architecture
 and the ISE component is thightened up so as to allow the ISE to overcome the register 
-I/O limitations, however these approaches tackle the problem for a compiler/simulation 
+I/O limitations, however these approaches generally tackle the problem for a compiler/simulation 
 point of view and not address the problem of generating synthesizable representations for 
 these models.