Changeset 99 for anr/section-2.tex

Timestamp:

Feb 8, 2010, 12:11:05 AM (15 years ago)

Author:

coach

Message:

IA: 1) mise en page et verification de 2, 2.1, 2.2 4.1. 2) entrer bull/xilinx/navtel dans 6.1 3) xilinx dans 7.

File:

• anr/section-2.tex (modified) (5 diffs)

anr/section-2.tex

@@ -1 @@
-The first objective of COACH is to provide SMEs (Small and Medium Enterprises) an open-source framework to
-design embedded system on FPGA devices. 
-
+Embedded systems (SoC and MPSoC) became an inevitable evolution in microelectronic industry.
 Due to the exploding fabrication costs, the ASIC technology (Application Specific Integrated Circuit) 
-is not an option for most SMEs. Fortunately, the new FPGA (Field Programmable Gate Array) components,
-such as the Virtex5 family from Xilinx, or the Stratix4 family from Altera can implement a complete
-multi-processor architecture on a single chip.
-
-%But the design of a SoC (System on Chip) or MPSoC (Multi-Processor System on Chip) is a complex
-%task, requiring adequate design methods to efficiently model, explore, and analyze the 
-%interactions between the software application and the hardware architectures. Moreover, most SMEs do not have 
-%in-home expertise in the field of hardware design or VHDL/Verilog modeling.
-%In order to meet the increasing performance requirements, to decrease the development cost, and to
-%shorten the time-to-market, they need new design methodologies. 
-
+is not an option for SMEs (Small and Medium Enterprises).
+Fortunately, the new FPGA (Field Programmable Gate Array) components,
+such as the Virtex5 family from \xilinx, or the Stratix4 family from \altera can implement a complete
+multi-processor architecture on a single device.
+But the design of embedded system is a long and complex task that requires expertise in software,
+software/hardware partionning, operating system, hardware design, VHDL/Verilog modeling.
+Only very few SMEs have these multiple expertises and are present on the embedded system market.
+\begin{center}\begin{minipage}{.8\linewidth}\textit{
+The major objective of COACH is to provide to SMEs an open-source framework to design
+embedded systems on FPGA devices.
+}\end{minipage}\end{center}
 %Current design methodologies provide quite low-level abstraction capabilities, and 
 %there is an urgent need to leverage system level exploration through the use of a high-level 
 %specification of the application and  design space exploration tools.
-
 %The first system oriented approaches are appearing, among which those
 %based on C/C++ and SystemC are the most popular, but few of them are specifically targetting FPGAs.
-
+%%%
+\parlf
 The COACH project will leverage on the expertise gained in the field of virtual prototyping
 with the SoCLib platform, to propose a new design flow based on a small number of architectural templates.
@@ -29 +27 @@
 template can be enriched by dedicated hardware coprocessors, obtained by high level synthesis (HLS) tools.
 During this project, the COACH partners will develop three different architectural templates:
-
 \begin{enumerate}
 \item An \altera architectural template based on the \altera IP core library and the AVALON system bus.
-\item A \xilinx architectural template based on the Xlinx IP core library and the OPB system bus.
-\item A Neutral architectural template based on the SoCLib IP core library and the VCI/OCP communication infrastructure.
+\item A \xilinx architectural template based on the \xilinx IP core library and the PLB system bus.
+\item A Neutral architectural template based on the SoCLib IP core library and the VCI/OCP
+      communication infrastructure.
 \end{enumerate}
-
 The proposed design flow starts from a high level description of the application, specified as a set of 
 parallel tasks written in C, without any assumption on the hardware or software implementation
 of these tasks. It let the system
-designer in charge of expessing the coarse grain parallelism of the application, gives the designer
+designer in charge of expressing the coarse grain parallelism of the application, gives the designer
 the possibility to explore various mapping of the application on the selected template architecture,
 and offers a high predictability of results with respect to cost and performance objectives.
-
+\\
 When this interactive, system level, design space exploration is completed (converging to
 a specific mapping on a specific version of the selected architectural template), the rest of the flow 
@@ -48 +45 @@
 code for the software running on the embedded processors, and the bit-stream to program the the target FPGA 
 will be automatically generated by the COACH tools.
-
-\par
+%
+\parlf
 The strength of the COACH approach is the strong integration of the high-level synthesis tools 
 in a plat-form based design flow supporting virtual prototyping and design space exploration.
@@ -60 +57 @@
 %in Paris from january 2009 to february 2010, to analyse the issues of interfacing and integrating
 %those various technologies, and to define the detailed architecture of the proposed design flow.
-\par
-
+%%%
+\parlf
+In HPC (High Performance Computing), the kind of targeted application is an existing one
+running on a PC.
+The COACH framework helps designer to accelerate it by migrating critical parts into a
+SoC embedded into an FPGA device plugged to the PC PCI/X bus.
+\begin{center}\begin{minipage}{.8\linewidth}\textit{
+The second objective of COACH is to extend the framework to HPC.
+}\end{minipage}\end{center}
+This will allow SMEs to enter HPC market for the applications that are
+unadapted to the current GPU based solutions.
+%%%
+\parlf
 In summary, the COACH project is clearly oriented toward industry, even if most technology building blocks
 have been previously developed by academic laboratories.
@@ -98 +106 @@
 %Every point of the design space can be implemented on any FPGA component,
 %as long as it contains the hardware ressources required by the selected architectural template.
-%Basically, COACH will support both Altera and Xilinx FPGA families.
+%Basically, COACH will support both \altera and \xilinx FPGA families.
 %\end{itemize}
 %